8.3.1 SMBus Interface

The BQ24725A operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The BQ24725A uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The BQ24725A uses the SMBus Read-Word and Write-Word protocols (see Figure 11) to communicate with the smart battery. The BQ24725A performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the BQ24725A has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus communication is enabled with the following conditions:

• V_VCC is above UVLO;
• V_ACDET is above 0.6V;

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a START condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 12 and Figure 13 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the BQ24725A because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The BQ24725A supports the charger commands as described in Table 2.

Figure 11. SMBus Write-Word and Read-Word Protocols

Figure 12. SMBus Write Timing

Figure 13. SMBus Read Timing