The switching node rise and fall times
should be minimized for minimum switching loss. Proper layout of the components to
minimize high frequency current path loop (see Figure 12-1)
is important to prevent electrical and magnetic field radiation and high frequency
resonant problems. Follow this specific order carefully to achieve the proper
- Place input capacitor as close as
possible to PMID pin and use shortest thick copper trace to connect input
capacitor to PMID pin and GND plane.
- It is critical that the exposed
thermal pad on the backside of the device be soldered to the PCB ground. Ensure
that there are sufficient thermal vias directly under the IC, connecting to the
ground plane on the other layers. Connect the GND pins to thermal pad on the top
- Put output capacitor near to the
inductor output terminal and the charger device. Ground connections need to be
tied to the IC ground with a short copper trace or GND plane
- Place inductor input terminal to SW pin as close as possible
and limit SW node copper area to lower electrical and magnetic field radiation.
Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
- Route analog ground separately from power ground if possible.
Connect analog ground and power ground together using thermal pad as the single
ground connection point under the charger device. It is acceptable to connect
all grounds to a single ground plane if multiple ground planes are not
- Decoupling capacitors should be
placed next to the device pins and make trace connection as short as
- For high
input voltage and high charge current applications, sufficient copper area on
GND should be budgeted to dissipate heat from power losses.
- Ensure that the number and sizes of vias allow enough copper
for a given current path
- See the 2 layer PCB design
example in Figure 12-2 for the recommended component placement with trace,
grounding and via locations.
Figure 12-1 High
Frequency Current Path