JAJSFS8 July   2018 BQ25601D

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     アプリケーション概略図
  4. 改訂履歴
  5. 概要(続き)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On-Reset (POR)
      2. 9.3.2 Device Power Up from Battery without Input Source
      3. 9.3.3 Power Up from Input Source
        1. 9.3.3.1 Power Up REGN Regulation
        2. 9.3.3.2 Poor Source Qualification
        3. 9.3.3.3 Input Source Type Detection
          1. 9.3.3.3.1 D+/D– Detection Sets Input Current Limit in BQ25601D
        4. 9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.3.3.5 Converter Power-Up
      4. 9.3.4 Boost Mode Operation From Battery
      5. 9.3.5 Host Mode and Standalone Power Management
        1. 9.3.5.1 Host Mode and Default Mode in BQ25601D
      6. 9.3.6 Power Path Management
      7. 9.3.7 Battery Charging Management
        1. 9.3.7.1 Autonomous Charging Cycle
        2. 9.3.7.2 Battery Charging Profile
        3. 9.3.7.3 Charging Termination
        4. 9.3.7.4 Thermistor Qualification
        5. 9.3.7.5 JEITA Guideline Compliance During Charging Mode
        6. 9.3.7.6 Boost Mode Thermistor Monitor during Battery Discharge Mode
        7. 9.3.7.7 Charging Safety Timer
    4. 9.4 Device Functional Modes
      1. 9.4.1 Narrow VDC Architecture
      2. 9.4.2 Dynamic Power Management
      3. 9.4.3 Supplement Mode
      4. 9.4.4 Shipping Mode and QON Pin
        1. 9.4.4.1 BATFET Disable Mode (Shipping Mode)
        2. 9.4.4.2 BATFET Enable (Exit Shipping Mode)
        3. 9.4.4.3 BATFET Full System Reset
        4. 9.4.4.4 QON Pin Operations
      5. 9.4.5 Status Outputs (PG, STAT, INT)
        1. 9.4.5.1 Power Good indicator ( PGPin PG_STAT Bit)
        2. 9.4.5.2 Charging Status indicator (STAT)
        3. 9.4.5.3 Interrupt to Host (INT)
    5. 9.5 Protections
      1. 9.5.1 Voltage and Current Monitoring in Converter Operation
        1. 9.5.1.1 Voltage and Current Monitoring in Buck Mode
          1. 9.5.1.1.1 Input Overvoltage (ACOV)
          2. 9.5.1.1.2 System Overvoltage Protection (SYSOVP)
      2. 9.5.2 Voltage and Current Monitoring in Boost Mode
        1. 9.5.2.1 VBUS Soft Start
        2. 9.5.2.2 VBUS Output Protection
        3. 9.5.2.3 Boost Mode Overvoltage Protection
      3. 9.5.3 Thermal Regulation and Thermal Shutdown
        1. 9.5.3.1 Thermal Protection in Buck Mode
        2. 9.5.3.2 Thermal Protection in Boost Mode
      4. 9.5.4 Battery Protection
        1. 9.5.4.1 Battery overvoltage Protection (BATOVP)
        2. 9.5.4.2 Battery Over-Discharge Protection
        3. 9.5.4.3 System Over-Current Protection
    6. 9.6 Programming
      1. 9.6.1 Serial Interface
        1. 9.6.1.1 Data Validity
        2. 9.6.1.2 START and STOP Conditions
        3. 9.6.1.3 Byte Format
        4. 9.6.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.6.1.5 Slave Address and Data Direction Bit
        6. 9.6.1.6 Single Read and Write
        7. 9.6.1.7 Multi-Read and Multi-Write
    7. 9.7 Register Maps
      1. 9.7.1  REG00 (address = 00) [reset = 00010111]
        1. Table 6. REG00 Field Descriptions
      2. 9.7.2  REG01 (address = 01) [reset = 00011010]
        1. Table 7. REG01 Field Descriptions
      3. 9.7.3  REG02 (address = 02) [reset = 10100010]
        1. Table 8. REG02 Field Descriptions
      4. 9.7.4  REG03 (address = 03) [reset = 00100010]
        1. Table 9. REG03 Field Descriptions
      5. 9.7.5  REG04 (address = 04) [reset = 01011000]
        1. Table 10. REG04 Field Descriptions
      6. 9.7.6  REG05 (address = 05) [reset = 10011111]
        1. Table 11. REG05 Field Descriptions
      7. 9.7.7  REG06 (address = 06) [reset = 01100110]
        1. Table 12. REG06 Field Descriptions
      8. 9.7.8  REG07 (address = 07) [reset = 01001100]
        1. Table 13. REG07 Field Descriptions
      9. 9.7.9  REG08 (address = 08) [reset = xxxxxxxx]
        1. Table 14. REG08 Field Descriptions
      10. 9.7.10 REG09 (address = 09) [reset = xxxxxxxx]
        1. Table 15. REG09 Field Descriptions
      11. 9.7.11 REG0A (address = 0A) [reset = xxxxxx00]
        1. Table 16. REG0A Field Descriptions
      12. 9.7.12 REG0B (address = 0B) [reset = 00111xxx]
        1. Table 17. REG0B Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
        1. 13.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

RTW Package
24-Pin WQFN
Top View
BQ25601D wqfn_24pin_slusda2.gif

Pin Functions

Pin TYPE(1) DESCRIPTION
NAME NO.
BAT 13 P Battery connection point to the positive terminal of the battery pack. The internal BATFET and current sensing is connected between SYS and BAT. Connect a 10 µF close to the BAT pin.
14
BTST 21 P PWM high side driver positive supply. Internally, the BTST pin is connected to the cathode of the boost-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
CE 9 DI Charge enable pin. When this pin is driven low, battery charging is enabled.
GND 17 Ground pins.
18
INT 7 DO Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin sends an active low, 256-µs pulse to host to report charger device status and fault.
NC 8 No Connect. Keep the pins float.
10
D– 3 AIO Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors
PMID 23 DO Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Put 10 μF ceramic capacitor on PMID to GND.
D+ 2 AIO Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors
QON 12 DI BATFET enable/reset control input. When BATFET is in ship mode, a logic low of tSHIPMODE duration turns on BATFET to exit shipping mode. When VBUS is not pluggeD–in, a logic low of tQON_RST (minimum 8 s) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enable BATFET to provide full system power reset. The pin contains an internal pull-up to maintain default high logic.
REGN 22 P LSFET driver and internal supply output. Internally, REGN is connected to the anode of the boost-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to GND. The capacitor should be placed close to the IC.
SCL 5 DI I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA 6 DIO I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
STAT 4 DO Open-drain charge status output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates charger status. Collect a current limit resister and a LED from a rail to this pin.
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): 1-Hz, 50% duty cycle Pulses
This pin can be disabled via EN_ICHG_MON[1:0] register bits.
SW 19 P Switching node output. Connected to output inductor. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
20
SYS 15 P Converter output connection point. The internal current sensing network is connected between SYS and BAT. Connect a 20 µF capacitor close to the SYS pin.
16
TS 11 AI Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and connect a 10-kΩ resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.
VAC 24 AI Charge input voltage sense. This pin must be connected to VBUS pin.
VBUS 1 P Charger input. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID pins. Place a 1-uF ceramic capacitor from VBUS to GND close to device.
Thermal Pad P Thermal pad and ground reference. This pad is ground reference for the device and it is also the thermal pad used to conduct heat from the device. This pad should be tied externally to a ground plane through PCB vias under the pad.
AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power