JAJSFS8 July   2018 BQ25601D

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     アプリケーション概略図
  4. 改訂履歴
  5. 概要(続き)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On-Reset (POR)
      2. 9.3.2 Device Power Up from Battery without Input Source
      3. 9.3.3 Power Up from Input Source
        1. 9.3.3.1 Power Up REGN Regulation
        2. 9.3.3.2 Poor Source Qualification
        3. 9.3.3.3 Input Source Type Detection
          1. 9.3.3.3.1 D+/D– Detection Sets Input Current Limit in BQ25601D
        4. 9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.3.3.5 Converter Power-Up
      4. 9.3.4 Boost Mode Operation From Battery
      5. 9.3.5 Host Mode and Standalone Power Management
        1. 9.3.5.1 Host Mode and Default Mode in BQ25601D
      6. 9.3.6 Power Path Management
      7. 9.3.7 Battery Charging Management
        1. 9.3.7.1 Autonomous Charging Cycle
        2. 9.3.7.2 Battery Charging Profile
        3. 9.3.7.3 Charging Termination
        4. 9.3.7.4 Thermistor Qualification
        5. 9.3.7.5 JEITA Guideline Compliance During Charging Mode
        6. 9.3.7.6 Boost Mode Thermistor Monitor during Battery Discharge Mode
        7. 9.3.7.7 Charging Safety Timer
    4. 9.4 Device Functional Modes
      1. 9.4.1 Narrow VDC Architecture
      2. 9.4.2 Dynamic Power Management
      3. 9.4.3 Supplement Mode
      4. 9.4.4 Shipping Mode and QON Pin
        1. 9.4.4.1 BATFET Disable Mode (Shipping Mode)
        2. 9.4.4.2 BATFET Enable (Exit Shipping Mode)
        3. 9.4.4.3 BATFET Full System Reset
        4. 9.4.4.4 QON Pin Operations
      5. 9.4.5 Status Outputs (PG, STAT, INT)
        1. 9.4.5.1 Power Good indicator ( PGPin PG_STAT Bit)
        2. 9.4.5.2 Charging Status indicator (STAT)
        3. 9.4.5.3 Interrupt to Host (INT)
    5. 9.5 Protections
      1. 9.5.1 Voltage and Current Monitoring in Converter Operation
        1. 9.5.1.1 Voltage and Current Monitoring in Buck Mode
          1. 9.5.1.1.1 Input Overvoltage (ACOV)
          2. 9.5.1.1.2 System Overvoltage Protection (SYSOVP)
      2. 9.5.2 Voltage and Current Monitoring in Boost Mode
        1. 9.5.2.1 VBUS Soft Start
        2. 9.5.2.2 VBUS Output Protection
        3. 9.5.2.3 Boost Mode Overvoltage Protection
      3. 9.5.3 Thermal Regulation and Thermal Shutdown
        1. 9.5.3.1 Thermal Protection in Buck Mode
        2. 9.5.3.2 Thermal Protection in Boost Mode
      4. 9.5.4 Battery Protection
        1. 9.5.4.1 Battery overvoltage Protection (BATOVP)
        2. 9.5.4.2 Battery Over-Discharge Protection
        3. 9.5.4.3 System Over-Current Protection
    6. 9.6 Programming
      1. 9.6.1 Serial Interface
        1. 9.6.1.1 Data Validity
        2. 9.6.1.2 START and STOP Conditions
        3. 9.6.1.3 Byte Format
        4. 9.6.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.6.1.5 Slave Address and Data Direction Bit
        6. 9.6.1.6 Single Read and Write
        7. 9.6.1.7 Multi-Read and Multi-Write
    7. 9.7 Register Maps
      1. 9.7.1  REG00 (address = 00) [reset = 00010111]
        1. Table 6. REG00 Field Descriptions
      2. 9.7.2  REG01 (address = 01) [reset = 00011010]
        1. Table 7. REG01 Field Descriptions
      3. 9.7.3  REG02 (address = 02) [reset = 10100010]
        1. Table 8. REG02 Field Descriptions
      4. 9.7.4  REG03 (address = 03) [reset = 00100010]
        1. Table 9. REG03 Field Descriptions
      5. 9.7.5  REG04 (address = 04) [reset = 01011000]
        1. Table 10. REG04 Field Descriptions
      6. 9.7.6  REG05 (address = 05) [reset = 10011111]
        1. Table 11. REG05 Field Descriptions
      7. 9.7.7  REG06 (address = 06) [reset = 01100110]
        1. Table 12. REG06 Field Descriptions
      8. 9.7.8  REG07 (address = 07) [reset = 01001100]
        1. Table 13. REG07 Field Descriptions
      9. 9.7.9  REG08 (address = 08) [reset = xxxxxxxx]
        1. Table 14. REG08 Field Descriptions
      10. 9.7.10 REG09 (address = 09) [reset = xxxxxxxx]
        1. Table 15. REG09 Field Descriptions
      11. 9.7.11 REG0A (address = 0A) [reset = xxxxxx00]
        1. Table 16. REG0A Field Descriptions
      12. 9.7.12 REG0B (address = 0B) [reset = 00111xxx]
        1. Table 17. REG0B Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
        1. 13.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

REG07 (address = 07) [reset = 01001100]

Figure 35. Register REG07
7 6 5 4 3 2 1 0
IINDET_EN TMR2X_EN BATFET_DIS JEITA_VSET BATFET_DLY BATFET_RST_EN VDPM_BAT_TRACK[1] VDPM_BAT_TRACK[0]
R/W R/W R/W R/W R/W R/W R/W R/W

Table 13. REG07 Field Descriptions

Bit Field POR Type(1) Reset Description Comment
7 IINDET_EN 0 R/W by REG_RST
by Watchdog

0 - Not in input current limit detection
1 - Force input current limit detection when VBUS is present
Returns to 0 after input detection is complete
6 TMR2X_EN 1 R/W by REG_RST
by Watchdog
0 – Disable
1 – Safety timer slowed by 2X during input DPM (both V and I) or JEITA cool, or thermal regulation
5 BATFET_DIS 0 R/W by REG_RST 0 – Allow Q4 turn on, 1 – Turn off Q4 with tBATFET_DLY delay time (REG07[3]) Default: Allow Q4 turn on(0)
4 JEITA_VSET
(45C-60C)
0 R/W by REG_RST
by Watchdog
0 – Set Charge Voltage to 4.1V ( max),
1 – Set Charge Voltage to VREG
3 BATFET_DLY 1 R/W by REG_RST 0 – Turn off BATFET immediately when BATFET_DIS bit is set
1 –Turn off BATFET after tBATFET_DLY (typ. 10 s) when BATFET_DIS bit is set
Default: 1
Turn off BATFET after tBATFET_DLY (typ. 10 s) when BATFET_DIS bit is set
2 BATFET_RST_EN 1 R/W by REG_RST
by Watchdog
0 – Disable BATFET reset function
1 – Enable BATFET reset function
Default: 1
Enable BATFET reset function
1 VDPM_BAT_TRACK[1] 0 R/W by REG_RST 00 - Disable function (VINDPM set by register)
01 - VBAT + 200mV
10 - VBAT + 250mV
11 - VBAT + 300mV
Sets VINDPM to track BAT voltage. Actual VINDPM is higher of register value and VBAT + VDPM_BAT_TRACK
0 VDPM_BAT_TRACK[0] 0 R/W by REG_RST
LEGEND: R/W = Read/Write; R = Read only