SLUSE13A January 2020 – May 2021 BQ76952
The SPI interface in the BQ76952 device operates as a responder-only interface with an optional CRC check. If the OTP has not been programmed, the BQ76952 device initially powers up by default in 400 kHz I2C mode, while other device versions will initially powerup by default in SPI mode with CRC enabled, as described in the Device Comparison Table. The OTP setting to select SPI mode can be programmed into the BQ76952 on the manufacturing line, then when the device powers up, it automatically enters SPI mode. The host can also change the serial communication setting while in CONFIG_UPDATE mode, although the device will not immediately change communication mode upon exit of CONFIG_UPDATE mode to avoid losing communications during evaluation or production. The host can reset the device or write the SWAP_TO_SPI() subcommand to change the communications interface to SPI immediately.
The SPI interface logic operates with clock polarity (CPOL) = 0 and clock phase (CPHA) = 0, as shown in the figure below.
The device also includes an optional 8-bit CRC using polynomial x8+x2+x+1. The interface must use 16-bit transactions if CRC is not enabled, and must use 24-bit transactions when CRC is enabled. CRC mode is enabled or disabled based on the setting of Settings:Configuration:Comm Type. Based on configuration settings, the logic will:
(a) Only work with CRC, will not accept data without valid CRC, or
(b) Only accept transactions without CRC (so the host must only clock 16-bits per transaction, the device will detect an error if more or less clocks are sent).
If the host performs a write with CRC and the CRC is not correct, then the incoming data is not transferred to the incoming buffer, and the outgoing buffer (used for the next transaction) is also reset to 0xFFFF. This transaction is considered invalid. On the next transaction, the CRC (if clocked out) will be 0xAA, so the 0xFFFFAA will indicate to the controller that a CRC error was detected.
The internal oscillator in the BQ76952 device may not be running when the host initiates a transaction (for example, this can occur if the device is in SLEEP mode). If this occurs, the interface will drive out 0xFFFF on SPI_MISO for the first 16-bits clocked out. It will also drive out 0xFF for the third (CRC) byte as well, if CRC is enabled. So the 0xFFFF or 0xFFFFFF will indicate to the controller that the internal oscillator is not ready yet.
The device will automatically wake the internal oscillator at a falling edge of SPI_CS, but it may take up to 50 µs to stabilize and be available for use to the SPI interface logic. The address 0x7F used in the device is defined in such a manner that there should be no valid transaction to write 0xFF into this address. Thus the two-byte pattern 0xFFFF should never occur as a valid sequence in the first two bytes of a transaction (that is, it is only used as a flag that something is wrong, similar to an I2C NACK).
Due to the delay in the HFO powering up if initially off, the device includes a programmable hysteresis to cause the HFO to stay powered for a programmable number of seconds after it is wakened by a falling edge on SPI_CS. This hysteresis is controlled by the Settings:Configuration:Comm Idle Time configuration setting, which can be set from 0 to 255 seconds (while in SPI mode, the device will use a minimum hysteresis of 1 second even if the value is set to 0). The host can set this to a longer time (up to 255 seconds) and maintain regular communications within this time window, causing the HFO to stay powered, so the device can respond quickly to SPI transactions. However, keeping the HFO running continuously will cause the device to consume additional supply current beyond what it would consume if the HFO were only powered when needed (the HFO draws ≈30 µA when powered). To avoid this extra supply current, the host can send an initial, unnecessary SPI transaction to cause the HFO to waken, and retry this until a valid response is returned on SPI_MISO. At this point, the host can begin sending the intended SPI transactions.
If an excessive number of SPI transactions occur over a long period of time, the device may experience a watchdog fault. It is recommended to limit the frequency of SPI transactions by providing 50 μs or more from the end of one transaction to the start of a new transaction.
The device includes ability to detect a frozen or disconnected SPI bus condition, and it will then reset the bus logic. This condition is recognized when the SPI_CS is low and the SPI_SCLK is static and not changing for a two second timeout.
Depending on the version of the device being used, the SPI_MISO pin may be configured by default to use the REG18 LDO for its output drive, which will result in a 1.8-V signal level. This may cause communications errors if the host processor operates with a higher voltage, such as 3.3 V or 5 V. The SPI_MISO pin can be programmed to instead use the REG1 LDO for its output drive by setting the Settings:Configuration:SPI Configuration[MISO_REG1] data memory configuration bit. This bit should only be set if the REG1 LDO is powered. After this bit has been modified, it is necessary to send the SWAP_TO_SPI() or SWAP_COMM_MODE() subcommands for the device to use the new value.
The device includes optional pin filtering on the SPI input pins, which implements a filter with approximately 200 ns delay on each input pin. This filtering is enabled by default but can be disabled by clearing the Settings:Configuration:SPI Configuration[FILT] data memory configuration bit.