SLUSE13A January 2020 – May 2021 BQ76952
The high-side CHG and DSG FET drivers operate differently when they are triggered to turn off their respective FET. The CHG driver includes an internal switch which discharges the CHG pin toward the BAT pin level. The DSG FET driver will discharge the DSG pin toward the LD pin level, but it includes a more complex structure than just a switch, to support a faster turn off.
When the DSG driver is triggered to turn off, the device will initially begin discharging the DSG pin toward VSS. However, since the PACK+ terminal may not fall to a voltage near VSS quickly, the DSG FET gate should not be driven significantly below PACK+, otherwise the DSG FET may be damaged due to excessive negative gate-source voltage. Thus, the device monitors the voltage on the LD pin (which is connected to PACK+ through an external series resistor) and will stop the discharge when the DSG pin voltage drops below the LD pin voltage. When the discharge has stopped, the DSG pin voltage may relax back above the LD pin voltage, at which point the device will again discharge the DSG pin toward VSS, until the DSG gate voltage again falls below the LD pin voltage. This repeats in a series of pulses which over time discharge the DSG gate to the voltage of the LD pin. This pulsing continues for approximately 100 to 200 μs, after which the driver remains in a high impedance state if within approximately 500 mV of the voltage of the LD pin. The external resistor between the DSG gate and source then discharges the remaining FET VGS voltage so the FET remains off.
The external series gate resistor between the DSG pin and the DSG FET gate is used to adjust the speed of the turn-off transient. A low resistance (such as 100 Ω) will provide a fast turn-off during a short circuit event, but this may result in an overly large inductive spike at the top of stack when the FET is disabled. A larger resistor value (such as 1 kΩ or 4.7 kΩ) will reduce this speed and the corresponding inductive spike level.
Oscilloscope captures of DSG driver turn-off are shown below, with the DSG pin driving the gate of a CSD19536KCS NFET, which has a typical Ciss of 9250 pF. Figure 16-6 shows the signals when using a 1 kΩ series gate resistor between the DSG pin and the FET gate, and a light load on PACK+, such that the voltage on PACK+ drops slowly as the FET is disabled. The pulsing on the DSG pin can be seen lasting for approximately 170 μs.
A zoomed-in version of the pulsing generated by the DSG pin is shown in Figure 16-7, this time with PACK+ shorted to the top of stack.
A slower turn-off case is shown in Figure 16-8, using a 4.7 kΩ series gate resistor, and the PACK+ connector shorted to the top of stack.
A fast turn-off case is shown in Figure 16-9, in which a 100 Ω series gate resistor is used between the DSG pin and the FET gate.