SLUSE13A January   2020  – May 2021 BQ76952

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information bq76952
    5. 7.5  Supply Current
    6. 7.6  Digital I/O
    7. 7.7  LD Pin
    8. 7.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 7.9  FUSE Pin Functionality
    10. 7.10 REG18 LDO
    11. 7.11 REG0 Pre-regulator
    12. 7.12 REG1 LDO
    13. 7.13 REG2 LDO
    14. 7.14 Voltage References
    15. 7.15 Coulomb Counter
    16. 7.16 Coulomb Counter Digital Filter (CC1)
    17. 7.17 Current Measurement Digital Filter (CC2)
    18. 7.18 Current Wake Detector
    19. 7.19 Analog-to-Digital Converter
    20. 7.20 Cell Balancing
    21. 7.21 Cell Open Wire Detector
    22. 7.22 Internal Temperature Sensor
    23. 7.23 Thermistor Measurement
    24. 7.24 Internal Oscillators
    25. 7.25 High-side NFET Drivers
    26. 7.26 Comparator-Based Protection Subsystem
    27. 7.27 Timing Requirements - I2C Interface, 100kHz Mode
    28. 7.28 Timing Requirements - I2C Interface, 400kHz Mode
    29. 7.29 Timing Requirements - HDQ Interface
    30. 7.30 Timing Requirements - SPI Interface
    31. 7.31 Interface Timing Diagrams
    32. 7.32 Typical Characteristics
  8. Device Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 BQ76952 Device Versions
    4. 8.4 Diagnostics
  9. Device Configuration
    1. 9.1 Commands and Subcommands
    2. 9.2 Configuration Using OTP or Registers
    3. 9.3 Device Security
    4. 9.4 Scratchpad Memory
  10. 10Measurement Subsystem
    1. 10.1  Voltage Measurement
      1. 10.1.1 Voltage Measurement Schedule
      2. 10.1.2 Usage of VC Pins for Cells Versus Interconnect
    2. 10.2  General Purpose ADCIN Functionality
    3. 10.3  Coulomb Counter and Digital Filters
    4. 10.4  Synchronized Voltage and Current Measurement
    5. 10.5  Internal Temperature Measurement
    6. 10.6  Thermistor Temperature Measurement
    7. 10.7  Factory Trim of Voltage ADC
    8. 10.8  Voltage Calibration (ADC Measurements)
    9. 10.9  Voltage Calibration (COV and CUV Protections)
    10. 10.10 Current Calibration
    11. 10.11 Temperature Calibration
  11. 11Primary and Secondary Protection Subsystems
    1. 11.1 Protections Overview
    2. 11.2 Primary Protections
    3. 11.3 Secondary Protections
    4. 11.4 High-Side NFET Drivers
    5. 11.5 Protection FETs Configuration and Control
      1. 11.5.1 FET Configuration
      2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
    6. 11.6 Load Detect Functionality
  12. 12Device Hardware Features
    1. 12.1  Voltage References
    2. 12.2  ADC Multiplexer
    3. 12.3  LDOs
      1. 12.3.1 Preregulator Control
      2. 12.3.2 REG1 and REG2 LDO Controls
    4. 12.4  Standalone Versus Host Interface
    5. 12.5  Multifunction Pin Controls
    6. 12.6  RST_SHUT Pin Operation
    7. 12.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
    8. 12.8  ALERT Pin Operation
    9. 12.9  DDSG and DCHG Pin Operation
    10. 12.10 Fuse Drive
    11. 12.11 Cell Open Wire
    12. 12.12 Low Frequency Oscillator
    13. 12.13 High Frequency Oscillator
  13. 13Device Functional Modes
    1. 13.1 Overview
    2. 13.2 NORMAL Mode
    3. 13.3 SLEEP Mode
    4. 13.4 DEEPSLEEP Mode
    5. 13.5 SHUTDOWN Mode
    6. 13.6 CONFIG_UPDATE Mode
  14. 14Serial Communications Interface
    1. 14.1 Serial Communications Overview
    2. 14.2 I2C Communications
    3. 14.3 SPI Communications
      1. 14.3.1 SPI Protocol
    4. 14.4 HDQ Communications
  15. 15Cell Balancing
    1. 15.1 Cell Balancing Overview
  16. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Design Requirements (Example)
      2. 16.2.2 Detailed Design Procedure
      3. 16.2.3 Application Performance Plot
      4. 16.2.4 Calibration Process
    3. 16.3 Random Cell Connection Support
    4. 16.4 Startup Timing
    5. 16.5 FET Driver Turn-Off
    6. 16.6 Unused Pins
  17. 17Power Supply Requirements
  18. 18Layout
    1. 18.1 Layout Guidelines
    2. 18.2 Layout Example
  19. 19Device and Documentation Support
    1. 19.1 Documentation Support
    2. 19.2 Support Resources
    3. 19.3 Trademarks
    4. 19.4 Electrostatic Discharge Caution
    5. 19.5 Glossary
  20. 20Mechanical, Packaging, Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

SHUTDOWN Mode

SHUTDOWN mode is the lowest power mode of the BQ76952, which can be used for shipping or long-term storage. In this mode, the device loses all register state information, the internal logic is powered down, the protection FETs are all disabled, so no voltage is provided at the battery pack terminals. All protections are disabled, all voltage, current, and temperature measurements are disabled, and no communications are supported. When the device exits SHUTDOWN, it will boot and read parameters stored in OTP (if that has been written). If the OTP has not been written, the device will power up with default settings, and then settings can be changed by the host writing device registers.

Entering SHUTDOWN mode involves a sequence of steps. The sequence can be initiated manually through the serial communications interface. The device can also be configured to enter SHUTDOWN mode automatically based on the top of stack voltage or the minimum cell voltage. If the top-of-stack voltage falls below a programmed stack voltage threshold, or if the minimum cell voltage falls below a programmed cell voltage threshold, the SHUTDOWN mode sequence is automatically initiated. The shutdown based on cell voltage does not apply to cell input pins being used to measure interconnect.

While the BQ76952 device is in NORMAL mode or SLEEP mode, the device can also be configured to enter SHUTDOWN mode if the internal temperature measurement exceeds a programmed temperature threshold for a programmed delay.

When the SHUTDOWN mode sequence has been initiated by subcommand or the RST_SHUT pin driven high for 1-sec, the device will wait for a delay then disable the protection FETs. After the delay from when the sequence begins, the device will enter SHUTDOWN mode. However, if the voltage on the LD pin is still above the VWAKEONLD level, shutdown will be delayed until the voltage on LD falls below that level.

While the device is in SHUTDOWN mode, a ≈5 V voltage is provided at the TS2 pin with high source impedance. If the TS2 pin is pulled low, such as by a switch to VSS, or if a voltage is applied at the LD pin above VWAKEONLD (such as when a charger is attached in series FET configuration), the device will exit SHUTDOWN mode. Note: if a thermistor is attached from the TS2 pin to VSS, this may prevent the device from ever fully entering SHUTDOWN mode.

As a countermeasure to avoid an unintentional wake from SHUTDOWN mode when putting the BQ76952 device into long-term storage, the device can be configured to automatically reenter SHUTDOWN mode after a programmed number of minutes.

The BQ76952 device performs periodic memory integrity checks and will force a watchdog reset if any corruption is detected. To avoid a cycle of resets in the case of a memory fault, the device will enter SHUTDOWN mode rather than resetting if a memory error is detected within a programmed number of seconds after a watchdog reset has occurred.

When the device is wakened from SHUTDOWN, it generally requires approximately 200-300 ms for the internal circuitry to power up, load settings from OTP memory, perform initial measurements, evaluate those relative to enabled protections, then to enable FETs if conditions allow. This can be much longer depending on settings.

The BQ76952 device integrates a hardware overtemperature detection circuit, which determines when the die temperature passes an excessive temperature of approximately 120°C. If this detector triggers, the device will automatically begin the sequence to enter SHUTDOWN if this functionality is enabled through configuration.