SLUSE13A January   2020  – May 2021 BQ76952

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information bq76952
    5. 7.5  Supply Current
    6. 7.6  Digital I/O
    7. 7.7  LD Pin
    8. 7.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 7.9  FUSE Pin Functionality
    10. 7.10 REG18 LDO
    11. 7.11 REG0 Pre-regulator
    12. 7.12 REG1 LDO
    13. 7.13 REG2 LDO
    14. 7.14 Voltage References
    15. 7.15 Coulomb Counter
    16. 7.16 Coulomb Counter Digital Filter (CC1)
    17. 7.17 Current Measurement Digital Filter (CC2)
    18. 7.18 Current Wake Detector
    19. 7.19 Analog-to-Digital Converter
    20. 7.20 Cell Balancing
    21. 7.21 Cell Open Wire Detector
    22. 7.22 Internal Temperature Sensor
    23. 7.23 Thermistor Measurement
    24. 7.24 Internal Oscillators
    25. 7.25 High-side NFET Drivers
    26. 7.26 Comparator-Based Protection Subsystem
    27. 7.27 Timing Requirements - I2C Interface, 100kHz Mode
    28. 7.28 Timing Requirements - I2C Interface, 400kHz Mode
    29. 7.29 Timing Requirements - HDQ Interface
    30. 7.30 Timing Requirements - SPI Interface
    31. 7.31 Interface Timing Diagrams
    32. 7.32 Typical Characteristics
  8. Device Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 BQ76952 Device Versions
    4. 8.4 Diagnostics
  9. Device Configuration
    1. 9.1 Commands and Subcommands
    2. 9.2 Configuration Using OTP or Registers
    3. 9.3 Device Security
    4. 9.4 Scratchpad Memory
  10. 10Measurement Subsystem
    1. 10.1  Voltage Measurement
      1. 10.1.1 Voltage Measurement Schedule
      2. 10.1.2 Usage of VC Pins for Cells Versus Interconnect
    2. 10.2  General Purpose ADCIN Functionality
    3. 10.3  Coulomb Counter and Digital Filters
    4. 10.4  Synchronized Voltage and Current Measurement
    5. 10.5  Internal Temperature Measurement
    6. 10.6  Thermistor Temperature Measurement
    7. 10.7  Factory Trim of Voltage ADC
    8. 10.8  Voltage Calibration (ADC Measurements)
    9. 10.9  Voltage Calibration (COV and CUV Protections)
    10. 10.10 Current Calibration
    11. 10.11 Temperature Calibration
  11. 11Primary and Secondary Protection Subsystems
    1. 11.1 Protections Overview
    2. 11.2 Primary Protections
    3. 11.3 Secondary Protections
    4. 11.4 High-Side NFET Drivers
    5. 11.5 Protection FETs Configuration and Control
      1. 11.5.1 FET Configuration
      2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
    6. 11.6 Load Detect Functionality
  12. 12Device Hardware Features
    1. 12.1  Voltage References
    2. 12.2  ADC Multiplexer
    3. 12.3  LDOs
      1. 12.3.1 Preregulator Control
      2. 12.3.2 REG1 and REG2 LDO Controls
    4. 12.4  Standalone Versus Host Interface
    5. 12.5  Multifunction Pin Controls
    6. 12.6  RST_SHUT Pin Operation
    7. 12.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
    8. 12.8  ALERT Pin Operation
    9. 12.9  DDSG and DCHG Pin Operation
    10. 12.10 Fuse Drive
    11. 12.11 Cell Open Wire
    12. 12.12 Low Frequency Oscillator
    13. 12.13 High Frequency Oscillator
  13. 13Device Functional Modes
    1. 13.1 Overview
    2. 13.2 NORMAL Mode
    3. 13.3 SLEEP Mode
    4. 13.4 DEEPSLEEP Mode
    5. 13.5 SHUTDOWN Mode
    6. 13.6 CONFIG_UPDATE Mode
  14. 14Serial Communications Interface
    1. 14.1 Serial Communications Overview
    2. 14.2 I2C Communications
    3. 14.3 SPI Communications
      1. 14.3.1 SPI Protocol
    4. 14.4 HDQ Communications
  15. 15Cell Balancing
    1. 15.1 Cell Balancing Overview
  16. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Design Requirements (Example)
      2. 16.2.2 Detailed Design Procedure
      3. 16.2.3 Application Performance Plot
      4. 16.2.4 Calibration Process
    3. 16.3 Random Cell Connection Support
    4. 16.4 Startup Timing
    5. 16.5 FET Driver Turn-Off
    6. 16.6 Unused Pins
  17. 17Power Supply Requirements
  18. 18Layout
    1. 18.1 Layout Guidelines
    2. 18.2 Layout Example
  19. 19Device and Documentation Support
    1. 19.1 Documentation Support
    2. 19.2 Support Resources
    3. 19.3 Trademarks
    4. 19.4 Electrostatic Discharge Caution
    5. 19.5 Glossary
  20. 20Mechanical, Packaging, Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Recommended Operating Conditions

Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBAT Supply voltage Voltage on BAT pin (normal operation) 4.7 80 V
VBAT Supply voltage(3) Voltage on BAT pin (OTP programming) 10 12 V
TOTP OTP programming temperature(3) -40 45 °C
VPORA Power-on reset Rising threshold on BAT 3 4 V
VPORA_HYS Power-on reset hysteresis Device shuts down when BAT < VPORA - VPORA_HYS 180 mV
VWAKEONLD Wake on LD voltage Rising edge on LD, with BAT already in valid range 0.8 1.45 2.25 V
VWAKEONTS2 Wake on TS2 voltage Falling edge on TS2, with BAT already in valid range. TS2 will be weakly driven with a ≈ 5 V level during shutdown. 0.7 1.1 V
VIN Input voltage range(3) PACK, LD 0 80 V
VIN Input voltage range(3) PCHG, PDSG the maximum of VBAT-9 or VLD-19 80 V
VIN Input voltage range(3) REG1, REG2, RST_SHUT, ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, except when the pin is being used for general purpose ADC input or thermistor measurement. 0 5.5 V
VIN Input voltage range(3) TS1, TS2, TS3, CFETOFF, DFETOFF, DCHG, DDSG, ALERT, HDQ, when the pin is configured for general purpose ADC input or thermistor measurement. 0 VREG18 V
VIN Input voltage range(3) SRP, SRN, SRP-SRN (while measuring current) –0.2 0.2 V
VIN Input voltage range(3) SRP, SRN (without measuring current) –0.2 0.75 V
VIN Input voltage range(3) (4) VVC(0) –0.2 0.5 V
VIN Input voltage range(3) VVC(x), 1 ≤ x ≤ 4 maximum of VVC(x–1) – 0.2 or VSS–0.2 minimum of VVC(x–1)+5.5 or VSS+80 V
VIN Input voltage range(3) VVC(x), x ≥ 5 maximum of VVC(x–1) – 0.2 or VSS + 2.0 minimum of VVC(x–1) + 5.5 or VSS + 80 V
RC External cell input resistance(3) (6) 20 100
CC External cell input capacitance(3) (6) 0.1 0.22 1 µF
VO Output voltage range LD 80 V
VO Output voltage range(5) CHG, DSG, CP1 85 V
TOPR Operating temperature(5) –40 85 °C
VCELL(ACC) Cell voltage measurement accuracy 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 25°C, 1 ≤ x ≤ 16(2) –5 5 mV
VCELL(ACC) Cell voltage measurement accuracy(5) 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 0°C to 60°C, 1 ≤ x ≤ 16(2) –10 10 mV
VCELL(ACC) Cell voltage measurement accuracy(5) –0.2 V < VVC(x) - VVC(x-1) < 5.5 V, TA = -40°C to 85°C, 1 ≤ x ≤ 16(2) –15 15 mV
VSTACK(ACC) Stack voltage (VC16 - VSS) measurement accuracy(5) 0 V < VVC16 - VVSS < 80 V, TA = -40°C to 85°C(2) –0.5 0.5 V
VPACK(ACC) PACK pin voltage measurement accuracy(5) 0 V < VPACK < 80 V, TA = -40°C to 85°C(2) –0.5 0.5 V
VLD(ACC) LD pin voltage measurement accuracy(5) 0 V < VLD < 80 V, TA = -40°C to 85°C(2) –0.5 0.5 V
Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage.
Specified by design
Voltage on VC0 can extend higher (limited by absolute maximum specification) during cell balancing.
Specified by characterization
Values may need to be optimized during system design and evaluation for best performance