JAJSEK1C August   2011  – August 2018 BUF20800-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 General-call Reset and Power-up
      2. 7.3.2 Output Voltage
      3. 7.3.3 Output Latch
      4. 7.3.4 Programmable VCOM
      5. 7.3.5 REFH and REFL Input range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Replacement of Traditional Gamma Buffer
      2. 7.4.2 Dynamic Gamma Control
    5. 7.5 Programming
      1. 7.5.1 Two-wire Bus Overview
      2. 7.5.2 Data Rates
      3. 7.5.3 Read/Write Operations
        1. 7.5.3.1 Writing
        2. 7.5.3.2 Reading
      4. 7.5.4 Register Maps
        1. 7.5.4.1 Addressing the BUF20800-Q1
      5. 7.5.5 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor Selection
        2. 8.2.2.2 REFH and REFL Voltage Settings
      3. 8.2.3 Application Curves
      4. 8.2.4 Configuration for 20 Gamma Channels
      5. 8.2.5 Configuration for 22 Gamma Channels
      6. 8.2.6 The BUF20800-Q1 in Industrial Applications
      7. 8.2.7 Total TI Panel Solution
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PowerPAD Design Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.3.2 Reading

Reading a DAC register will return the data stored in the DAC. This data can differ from the data stored in the DAC register. See the Output Latch section.

To read the DAC value:

  1. Send a START condition on the bus.
  2. Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
  3. Send the DAC address byte. Bits D7−D5 must be set to 0; Bits D4−D0 are the DAC address. Only DAC addresses 00000 to 10011 are valid and will be acknowledged.
  4. Send a START or STOP/START condition on the bus.
  5. Send correct device address and read/write bit = HIGH. The BUF20800-Q1 will acknowledge this byte.
  6. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte (bits D15−D8; only bits D9 and D8 have meaning); the next byte is the least significant byte (bits D7−D0).
  7. Acknowledge after receiving the first byte.
  8. Do not acknowledge the second byte to end the read transaction.

Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge.

To Read Multiple DACs:

  1. Send a START condition on the bus.
  2. Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
  3. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC will be the first in the sequence of DACs to be read. The BUF20800-Q1 will begin with this DAC and step through subsequent DACs in sequential order.
  4. Send a START or STOP/START condition on the bus.
  5. Send correct device address and read/write bit = HIGH. The BUF20800-Q1 will acknowledge this byte.
  6. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte (bits D15−D8, only bits D9 and D8 have meaning); the next byte is the least significant byte (bits D7−D0).
  7. Acknowledge after receiving each byte of data except for the last byte. The acknowledge bit of the last byte should be HIGH to end the read operation.
  8. When all desired DACs have been read, send a STOP or repeated START condition on the bus.

Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge.

BUF20800-Q1 write.gifFigure 12. Timing Diagram for Write DAC Register
BUF20800-Q1 read.gifFigure 13. Timing Diagram for Read DAC Register