SWRS109C May   2011  – December 2016 CC110L


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  General Characteristics
    5. 4.5  Current Consumption
      1. 4.5.1 Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz
      2. 4.5.2 Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz
    6. 4.6  Typical RX Current Consumption Over Temperature and Input Power Level, 868 or 915 MHz
    7. 4.7  RF Receive Section
      1. 4.7.1 Typical Sensitivity over Temperature and Supply Voltage, 868 MHz, Sensitivity Optimized Setting
      2. 4.7.2 Typical Sensitivity over Temperature and Supply Voltage, 915 MHz, Sensitivity Optimized Setting
      3. 4.7.3 Blocking and Selectivity
    8. 4.8  RF Transmit Section
      1. 4.8.1 Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz
      2. 4.8.2 Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz
    9. 4.9  Crystal Oscillator
    10. 4.10 Frequency Synthesizer Characteristics
    11. 4.11 DC Characteristics
    12. 4.12 Power-On Reset
    13. 4.13 Thermal Characteristics
    14. 4.14 Typical Characteristics
      1. 4.14.1 Typical Characteristics, RX Current Consumption
      2. 4.14.2 Typical Characteristics, Blocking and Selectivity
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
    4. 5.4  Configuration Software
    5. 5.5  4-wire Serial Configuration and Data Interface
    6. 5.6  Chip Status Byte
    7. 5.7  Register Access
    8. 5.8  SPI Read
    9. 5.9  Command Strobes
    10. 5.10 FIFO Access
    11. 5.11 PATABLE Access
    12. 5.12 Microcontroller Interface and Pin Configuration
      1. 5.12.1 Configuration Interface
      2. 5.12.2 General Control and Status Pins
    13. 5.13 Data Rate Programming
    14. 5.14 Receiver Channel Filter Bandwidth
    15. 5.15 Demodulator, Symbol Synchronizer, and Data Decision
      1. 5.15.1 Frequency Offset Compensation
      2. 5.15.2 Bit Synchronization
      3. 5.15.3 Byte Synchronization
    16. 5.16 Packet Handling Hardware Support
      1. 5.16.1 Packet Format
        1. Arbitrary Length Field Configuration
        2. Packet Length > 255
      2. 5.16.2 Packet Filtering in Receive Mode
        1. Address Filtering
        2. Maximum Length Filtering
        3. CRC Filtering
      3. 5.16.3 Packet Handling in Transmit Mode
      4. 5.16.4 Packet Handling in Receive Mode
      5. 5.16.5 Packet Handling in Firmware
    17. 5.17 Modulation Formats
      1. 5.17.1 Frequency Shift Keying
      2. 5.17.2 Amplitude Modulation
    18. 5.18 Received Signal Qualifiers and RSSI
      1. 5.18.1 Sync Word Qualifier
      2. 5.18.2 RSSI
      3. 5.18.3 Carrier Sense (CS)
        1. CS Absolute Threshold
        2. CS Relative Threshold
      4. 5.18.4 Clear Channel Assessment (CCA)
    19. 5.19 Radio Control
      1. 5.19.1 Power-On Start-Up Sequence
        1. Automatic POR
        2. Manual Reset
      2. 5.19.2 Crystal Control
      3. 5.19.3 Voltage Regulator Control
      4. 5.19.4 Active Modes (RX and TX)
      5. 5.19.5 RX Termination
      6. 5.19.6 Timing
        1. Overall State Transition Times
        2. Frequency Synthesizer Calibration Time
    20. 5.20 Data FIFO
    21. 5.21 Frequency Programming
    22. 5.22 VCO
      1. 5.22.1 VCO and PLL Self-Calibration
    23. 5.23 Voltage Regulators
    24. 5.24 Output Power Programming
    25. 5.25 General Purpose and Test Output Control Pins
    26. 5.26 Asynchronous and Synchronous Serial Operation
      1. 5.26.1 Asynchronous Serial Operation
      2. 5.26.2 Synchronous Serial Operation
    27. 5.27 System Considerations and Guidelines
      1. 5.27.1 SRD Regulations
      2. 5.27.2 Frequency Hopping and Multi-Channel Systems
      3. 5.27.3 Wideband Modulation when not Using Spread Spectrum
      4. 5.27.4 Data Burst Transmissions
      5. 5.27.5 Continuous Transmissions
      6. 5.27.6 Increasing Range
    28. 5.28 Configuration Registers
      1. 5.28.1 Configuration Register Details - Registers with preserved values in SLEEP state
      2. 5.28.2 Configuration Register Details - Registers that Loose Programming in SLEEP State
      3. 5.28.3 Status Register Details
    29. 5.29 Development Kit Ordering Information
  6. 6Applications, Implementation, and Layout
    1. 6.1 Bias Resistor
    2. 6.2 Balun and RF Matching
    3. 6.3 Crystal
    4. 6.4 Reference Signal
    5. 6.5 Additional Filtering
    6. 6.6 Power Supply Decoupling
    7. 6.7 PCB Layout Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation from Texas Instruments
      2. 7.2.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
    7. 7.7 Additional Acronyms
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information



Applications, Implementation, and Layout

The low cost application circuits (SWRR081 and SWRR082), which use multi layer inductors, are shown in Figure 6-1 and Figure 6-2 (see Table 6-1 for component values).

The designs in SWRR046 and SWRR045 were used for CC110L characterization. The 315 MHz and 433 MHz design SWRR046 use inexpensive multi-layer inductors similar to the low cost application circuit while the 868 MHz and 915 MHz design SWRR045 use wire-wound inductors. Wire-wound inductors give better output power and attenuation of harmonics compared to using multi-layer inductors.

Refer to design note DN032 SWRA346 for information about performance when using wire-wound inductors from different vendors. See also Design Note DN013 SWRA168, which gives the output power and harmonics when using multi-layer inductors. The output power is then typically +10 dBm when operating at 868/915 MHz.

Bias Resistor

The 56-kΩ bias resistor R171 is used to set an accurate bias current.

Balun and RF Matching

The balun and LC filter component values and their placement are important to keep the performance optimized. Gerber files and schematics for the reference designs are available for download from the TI website.

The components between the RF_N/RF_P pins and the point where the two signals are joined together (C131, C122, L122, and L132 in Figure 6-1 and L121, L131, C121, L122, C131, C122, and L132 in Figure 6-2) form a balun that converts the differential RF signal on CC110L to a single-ended RF signal. C124 is needed for DC blocking. L123, L124, and C123 (plus C125 in Figure 6-1) form a low-pass filter for harmonics attenuation.

The balun and LC filter components also matches the CC110L input impedance to a 50-Ω load. C126 provides DC blocking and is only needed if there is a DC path in the antenna. For the application circuit in Figure 6-2, this component may also be used for additional filtering, see Section 6.5.

CC110L typ_app_and_eval_circuit_swrs109.gif Figure 6-1 Typical Application and Evaluation Circuit 315 or 433 MHz
(Excluding Supply Decoupling Capacitors)
CC110L typ_app_and_eval_circuit_2_swrs109.gif Figure 6-2 Typical Application and Evaluation Circuit 868/915 MHz
(Excluding Supply Decoupling Capacitors)

Table 6-1 External Components

Component Value at 315 MHz Value at 433 MHz Value at 868/915 MHz
Without C127 and L125 With C127 and L125
C121 1 pF 1 pF
C122 6.8 pF 3.9 pF 1.5 pF 1.5 pF
C123 12 pF 8.2 pF 3.3 pF 3.3 pF
C124 220 pF 220 pF 100 pF 100 pF
C125 6.8 pF 5.6 pF
C126 220 pF 220 pF 100 pF 12 pF
C127 47 pF
C131 6.8 pF 3.9 pF 1.5 pF 1.5 pF
L121 12 nH 12 nH
L122 33 nH 27 nH 18 nH 18 nH
L123 18 nH 22 nH 12 nH 12 nH
L124 33 nH 27 nH 12 nH 12 nH
L125 3.3 nH
L131 12 nH 12 nH
L132 33 nH 27 nH 18 nH 18 nH


A crystal in the frequency range 26 - 27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C81 and C101) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals should equal CL for the crystal to oscillate at the specified frequency.

Equation 1. CC110L equat_1_swrs109.gif

The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasitic capacitance is typically 2.5 pF.

The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see Section 4.9).

The initial tolerance, temperature drift, aging and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application.

Avoid routing digital signals with sharp edges close to XOSC_Q1 PCB track or underneath the crystal dc operating point and result in duty cycle variation.

For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz.

Reference Signal

The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This input clock can either be a full- swing digital signal (0 V to VDD) or a sine wave of maximum 1 V peak-peak amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial capacitor. When using a full-swing digital signal, this capacitor can be omitted. The XOSC_Q2 line must be left un-connected. C81 and C101 can be omitted when using a reference signal.

Additional Filtering

In the 868/915 MHz reference design SWRR082, C127 and L125 together with C126 build an optional filter to reduce emission at carrier frequency - 169 MHz. This filter is necessary for applications with an external antenna connector that seek compliance with ETSI EN 300 220 V2.3.1. For more information, see DN017 SWRA168. If this filtering is not necessary, C126 will work as a DC block (only necessary if there is a DC path in the antenna). C127 and L125 should in that case be left unmounted. Additional external components (that is, an RF SAW filter) may be used in order to improve the performance in specific applications.

Power Supply Decoupling

The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance (SWRR081 and SWRR082 should be followed closely).

PCB Layout Recommendations

The top layer should be used for signal routing, and the open areas should be filled with metallization connected to ground using several vias.

The area under the chip is used for grounding and shall be connected to the bottom ground plane with several vias for good thermal performance and sufficiently low inductance to ground.

In SWRR081 and SWRR082, 5 vias are placed inside the exposed die attached pad. These vias should be “tented” (covered with solder mask) on the component side of the PCB to avoid migration of solder through the vias during the solder reflow process.

The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process, which may cause defects (splattering, solder balling). Using “tented” vias reduces the solder paste coverage below 100%. See Figure 6-3 for top solder resist and top paste masks.

Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC110L supply pin. Supply power filtering is very important.

Each decoupling capacitor ground pad should be connected to the ground plane by separate vias. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary. Routing in the ground plane underneath the chip or the balun/RF matching circuit, or between the chip's ground vias and the decoupling capacitor's ground vias should be avoided. This improves the grounding and ensures the shortest possible current return path.

Avoid routing digital signals with sharp edges close to XOSC_Q1 PCB track or underneath the crystal Q1 pad as this may shift the crystal dc operating point and result in duty cycle variation.

The external components should ideally be as small as possible (0402 is recommended) and surface mount devices are highly recommended. Components with different sizes than those specified may have differing characteristics.

Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry.

A CC11xL Development Kit with a fully assembled CC110L Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to get the best performance. The schematic, BOM and layout Gerber files are all available from the TI website (SWRR081 and SWRR082).

CC110L left_top_solder_resist_mask_swrs109.gif Figure 6-3 Left: Top Solder Resist Mask (Negative) – Right: Top Paste Mask. Circles are Vias