SWRS109C Data sheet

SWRS109C May 2011 – December 2016 CC110L

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5 Detailed Description

5.1 Overview

CC110L features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitized by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation, and bit/packet synchronization are performed digitally.

The transmitter part of CC110L is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO and a 90-degree phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode.

A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part.

A 4-wire SPI is used for configuration and data buffer access.

The digital baseband includes support for channel configuration, packet handling, and data buffering.

5.2 Functional Block Diagram

A simplified block diagram of CC110L is shown in Figure 5-1.

Figure 5-1 CC110L Simplified Block Diagram

5.3 Configuration Overview

CC110L can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. See Section 5.5 for more description of the SPI interface. The following key parameters can be programmed:

Power-down / power up mode
Crystal oscillator power-up / power-down
Receive / transmit mode
Carrier frequency / RF channel
Data rate
Modulation format
RX channel filter bandwidth
RF output power
Data buffering with separate 64-byte RX and TX FIFOs
Packet radio hardware support

Details of each configuration register can be found in Section 5.28.

Figure 5-2 shows a simplified state diagram that explains the main CC110L states together with typical usage and current consumption. For detailed information on controlling the CC110L state machine, and a complete state diagram, see Section 5.19.

CC110L simplified_radio_control_state_diagram_swrs109.gif

Figure 5-2 Simplified Radio Control State Diagram, with Typical Current Consumption at 1.2 kBaud Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized) – Frequency Band = 868 MHz

5.4 Configuration Software

CC110L can be configured using the SmartRF™ Studio software SWRC176. The SmartRF Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance and functionality.

After chip reset, all the registers have default values as shown Section 5.28.

The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface.

5.5 4-wire Serial Configuration and Data Interface

CC110L is configured through a simple 4-wire SPI-compatible interface (SI, SO, SCLK and CSn) where CC110L is the slave. This interface is also used to read and write buffered data. All transfers on the SPI interface are done most significant bit first.

All transactions on the SPI interface start with a header byte containing a R/W bit, a burst access bit (B), and a 6-bit address (A5–A0).

The CSn pin must be kept low during transfers on the SPI bus. If CSn goes high during the transfer of a header byte or during read/write from/to a register, the transfer will be cancelled. The timing for the address and data transfer on the SPI interface is shown in Figure 5-3 with reference to Table 5-1.

When CSn is pulled low, the MCU must wait until CC110L SO pin goes low before starting to transfer the header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low.

CC110L configuration_registers_write_and_read_swrs109.gif

Figure 5-3 Configuration Registers Write and Read Operations

Table 5-1 SPI Interface Timing Requirements

Parameter	Description		Min	Max	Units
f_SCLK	SCLK frequency		–	10	MHz
	100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).		–	10
	SCLK frequency, single access		–	9
	No delay between address and data byte		–	9
	SCLK frequency, burst access		–	6.5
	No delay between address and data byte, or between data bytes		–	6.5
t_sp,pd	CSn low to positive edge on SCLK, in power-down mode		150	–	µs
t_sp	CSn low to positive edge on SCLK, in active mode		20	–	ns
t_ch	Clock high		50	–	ns
t_cl	Clock low		50	–	ns
t_rise	Clock rise time		–	40	ns
t_fall	Clock fall time		–	40	ns
t_sd	Setup data (negative SCLK edge) to positive edge on SCLK (tsd applies between address and data bytes, and between data bytes)	Single access	55	–	ns
t_sd		Burst access	76	–	ns
t_hd	Hold data after positive edge on SCLK		20	–	ns
t_ns	Negative edge on SCLK to CSn high.		20	–	ns

NOTE

The minimum t_sp,pd figure in Table 5-1 can be used in cases where the user does not read the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power- down depends on the start-up time of the crystal being used. The 150 μs in Table 5-1 is the crystal oscillator start-up time measured on SWRR046 and SWRR045 using crystal AT-41CD2 from NDK.

5.6 Chip Status Byte

When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC110L on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal and this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running.

Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core are on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state. The RX state will be active when the chip is in receive mode. Likewise, TX is active when the chip is transmitting.

The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For read operations (the R/W bit in the header byte is set to 1), the FIFO_BYTES_AVAILABLE field contains the number of bytes available for reading from the RX FIFO. For write operations (the R/W bit in the header byte is set to 0), the FIFO_BYTES_AVAILABLE field contains the number of bytes that can be written to the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are available/free.

Table 5-2 gives a status byte summary.

Table 5-2 Status Byte Summary

Bits	Name	Description
7	CHIP_RDYn	Stays high until power and crystal have stabilized. Should always be low when using the SPI interface.
6:4	STATE[2:0]	Indicates the current main state machine mode
		Value	State	Description
		000	IDLE	IDLE state (Also reported for some transitional states instead of SETTLING or CALIBRATE)
		001	RX	Receive mode
		010	TX	Transmit mode
		011	FSTXON	Fast TX ready
		100	CALIBRATE	Frequency synthesizer calibration is running
		101	SETTLING	PLL is settling
		110	RXFIFO_OVERFLOW	RX FIFO has overflowed. Read out any useful data, then flush the FIFO with SFRX
		111	TXFIFO_UNDERFLOW	TX FIFO has underflowed. Acknowledge with SFTX
3:0	FIFO_BYTES_AVAILABLE[3:0]	The number of bytes available in the RX FIFO or free bytes in the TX FIFO

5.7 Register Access

The configuration registers on the CC110L are located on SPI addresses from 0x00 to 0x2E. Table 5-20 lists all configuration registers. It is highly recommended to use SmartRF Studio SWRC176 to generate optimum register settings. The detailed description of each register is found in Section 5.28.1 and Section 5.28.2. All configuration registers can be both written to and read. The R/W bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B) in the header byte. The address bits (A5 - A0) set the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high.

For register addresses in the range 0x30 - 0x3D, the burst bit is used to select between status registers when burst bit is one, and between command strobes when burst bit is zero (see Section 5.8). Because of this, burst access is not available for status registers and they must be accessed one at a time. The status registers can only be read.

5.8 SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (that is, MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC110L Errata Notes SWRZ037 for more details.

5.9 Command Strobes

Command Strobes may be viewed as single byte instructions to CC110L. By addressing a command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable calibration etc. The 11 command strobes are listed in Table 5-19.

NOTE

An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This means that if for example an SIDLE strobe is issued while the radio is in RX state, any other command strobes issued before the radio reaches IDLE state will be ignored.

The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D) are written. The R/W bit can be either one or zero and will determine how the FIFO_BYTES_AVAILABLE field in the status byte should be interpreted.

When writing command strobes, the status byte is sent on the SO pin.

A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRES strobe is being issued, one will have to wait for SO to go low again before the next header byte can be issued as shown in Figure 5-4. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes, which are executed when CSn goes high.

Figure 5-4 SRES Command Strobe

5.10 FIFO Access

The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the R/W bit is zero, the TX FIFO is accessed, and the RX FIFO is accessed when the R/W bit is one.

The TX FIFO is write-only, while the RX FIFO is read-only.

The burst bit is used to determine if the FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte, a new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high.

The following header bytes access the FIFOs:

0x3F: Single byte access to TX FIFO
0x7F: Burst access to TX FIFO
0xBF: Single byte access to RX FIFO
0xFF: Burst access to RX FIFO

When writing to the TX FIFO, the status byte (see Section 5.6) is output on SO for each new data byte as shown in Figure 5-3. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte received concurrently on SO will indicate that one byte is free in the TX FIFO. The TX FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe will flush the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TXFIFO_UNDERFLOW, or RXFIFO_OVERFLOW states. Both FIFOs are flushed when going to the SLEEP state.

Figure 5-5 gives a brief overview of different register access types possible.

5.11 PATABLE Access

The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects one or two data bytes after receiving the address (the burst bit must be set if two bytes are to be written). For OOK, two bytes should be written to PATABLE; the first byte after the address will set the logic 0 power level and the second byte written will set the logic 1 power level. For all other modulations formats, only one byte should be written to PATABLE. Use SmartRF Studio SWRC176 or DN013 SWRA168 for recommended register values for a given output power.

The PATABLE can also be read by setting the R/W bit to 1. The read operation can be done as a single byte or burst access, depending on how many bytes should be read (one or two). Note that pulling CSn high will reset the index counter to zero, meaning that burst access needs to be used for reading/writing the second PATABLE entry. For the same reason, if one byte is written to the PATABLE and this value is to be read out, CSn must be set high before the read access in order to set the index counter back to zero.

The content of the PATABLE is lost when entering the SLEEP state, except for the first byte, meaning that if OOK is used, the PATABLE needs to be reprogrammed when waking up from SLEEP.

CC110L register_access_types_swrs109.gif

Figure 5-5 Register Access Types

5.12 Microcontroller Interface and Pin Configuration

In a typical system, CC110L will interface to a microcontroller. This microcontroller must be able to:

Program CC110L into different modes
Read and write buffered data
Read back status information through the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn)

5.12.1 Configuration Interface

The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The SPI is described in Section 5.5.

5.12.2 General Control and Status Pins

The CC110L has two dedicated configurable pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 5.25 for more details on the signals that can be programmed.

GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options, the GDO1/SO pin will become a generic pin. When CSn is low, the pin will always function as a normal SO pin.

In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin while in transmit mode.

5.13 Data Rate Programming

The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency.

Equation 1. CC110L equat_2_swrs109.gif

The following approach can be used to find suitable values for a given data rate:

Equation 2. CC110L equat_3_swrs109.gif

Equation 3. CC110L equat_4_swrs109.gif

If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M = 0.

The data rate can be set from 0.6 kBaud to 500 kBaud with the minimum step size according to Table 5-3. See Section 4.4 for the minimum and maximum data rates for the different modulation formats.

Table 5-3 Data Rate Step Size (Assuming a 26-MHz Crystal)

Min Data Rate [kBaud]	Typical Data Rate [kBaud]	Max Data Rate [kBaud]	Data rate Step Size [kBaud]
0.6	1.0	0.79	0.0015
0.79	1.2	1.58	0.0031
1.59	2.4	3.17	0.0062
3.17	4.8	6.33	0.0124
6.35	9.6	12.7	0.0248
12.7	19.6	25.3	0.0496
25.4	38.4	50.7	0.0992
50.8	76.8	101.4	0.1984
101.6	153.6	202.8	0.3967
203.1	250	405.5	0.7935
406.3	500	500	1.5869

5.14 Receiver Channel Filter Bandwidth

In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth, which scales with the crystal oscillator frequency.

The following formula gives the relation between the register settings and the channel filter bandwidth:

Equation 4. CC110L equat_5_swrs109.gif

Table 5-4 lists the channel filter bandwidths supported by the CC110L.

Table 5-4 Channel Filter Bandwidths [kHz] (Assuming a 26-MHz Crystal)

MDMCFG4.CHANBW_M	MDMCFG4.CHANBW_E
MDMCFG4.CHANBW_M	00	01	10	11
00	812	406	203	102
01	650	325	162	81
10	541	270	135	68
11	464	232	116	58

For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel center tolerance due to crystal inaccuracy should also be subtracted from the channel filter bandwidth. The following example illustrates this:

With the channel filter bandwidth set to 500 kHz, the signal should stay within 80% of 500 kHz, which is 400 kHz. Assuming 915 MHz frequency and ±20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is ±40 ppm of 915 MHz, which is ±37 kHz. If the whole transmitted signal bandwidth is to be received within 400 kHz, the transmitted signal bandwidth should be maximum 400 kHz – 2×37 kHz, which is 326 kHz. By compensating for a frequency offset between the transmitter and the receiver, the filter bandwidth can be reduced and the sensitivity can be improved, see more in DN005 SWRA122 and in Section 5.15.1.

5.15 Demodulator, Symbol Synchronizer, and Data Decision

CC110L contains an advanced and highly configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see Section 5.18.2 for more information), the signal level in the channel is estimated. Data filtering is also included for enhanced performance.

5.15.1 Frequency Offset Compensation

The CC110L has a very fine frequency resolution (see Section 4.10). This feature can be used to compensate for frequency offset and drift.

When using 2-FSK, GFSK, or 4-FSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency within certain limits, by estimating the center of the received data. The frequency offset compensation configuration is controlled from the FOCCFG register. By compensating for a large frequency offset between the transmitter and the receiver, the sensitivity can be improved, see DN005 SWRA122.

The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG.FOC_LIMIT configuration register.

If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator will freeze until carrier sense asserts. This may be useful when the radio is in RX for long periods with no traffic, since the algorithm may drift to the boundaries when trying to track noise.

The tracking loop has two gain factors, which affects the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the gain before the sync word is detected, and FOCCFG.FOC_POST_K selects the gain after the sync word has been found

NOTE

Frequency offset compensation is not supported for OOK modulation.

The estimated frequency offset value is available in the FREQEST status register. This can be used for permanent frequency offset compensation. By writing the value from FREQEST into FSCTRL0.FREQOFF, the frequency synthesizer will automatically be adjusted according to the estimated frequency offset. More details regarding this permanent frequency compensation algorithm can be found in DN015 SWRA159.

5.15.2 Bit Synchronization

The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 5.13. Re-synchronization is performed continuously to adjust for error in the incoming symbol rate.

5.15.3 Byte Synchronization

Byte synchronization is achieved by a continuous sync word search. The sync word is a 16 bit configurable field (can be repeated to get a 32 bit) that is automatically inserted at the start of the packet by the modulator in transmit mode. The MSB in the sync word is sent first. The demodulator uses this field to find the byte boundaries in the stream of bits. The sync word will also function as a system identifier, since only packets with the correct predefined sync word will be received if the sync word detection in RX is enabled in register MDMCFG2 (see Section 5.18.1). The sync word detector correlates against the user-configured 16 or 32 bit sync word. The correlation threshold can be set to 15/16, 16/16, or 30/32 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is configured through the SYNC1 and SYNC0 registers.

5.16 Packet Handling Hardware Support

The CC110L has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler can be configured to add the following elements to the packet stored in the TX FIFO:

A programmable number of preamble bytes
A two byte synchronization (sync) word. Can be duplicated to give a 4-byte sync word (recommended). It is not possible to only insert preamble or only insert a sync word
A CRC checksum computed over the data field.
The recommended setting is 4-byte preamble and 4-byte sync word, except for 500 kBaud data rate where the recommended preamble length is 8 bytes.

In receive mode, the packet handling support will de-construct the data packet by implementing the following (if enabled):

Preamble detection
Sync word detection
CRC computation and CRC check
One byte address check
Packet length check (length byte checked against a programmable maximum length)

Optionally, two status bytes (see Table 5-5 and Table 5-6) with RSSI value and CRC status can be appended in the RX FIFO.

Table 5-5 Received Packet Status Byte 1 (First Byte Appended After the Data)

Bit	Field Name	Description
7:0	RSSI	RSSI value

Table 5-6 Received Packet Status Byte 2 (Second Byte Appended After the Data)

Bit	Field Name	Description
7	CRC_OK	1: CRC for received data OK (or CRC disabled) 0: CRC error in received data
6:0	Reserved

spacer

NOTE

5.16.1 Packet Format

The format of the data packet can be configured and consists of the following items (see Figure 5-6):

Preamble
Synchronization word
Optional length byte
Optional address byte
Payload
Optional 2 byte CRC

Figure 5-6 Packet Format

The preamble pattern is an alternating sequence of ones and zeros (10101010…). The minimum length of the preamble is programmable through the value of MDMCFG1.NUM_PREAMBLE. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue to send preamble bytes until the first byte is written to the TX FIFO. The modulator will then send the sync word and then the data bytes.

The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte sync word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by setting MDMCFG2.SYNC_MODE to 3 or 7. The sync word will then be repeated twice.

CC110L supports both constant packet length protocols and variable length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length mode must be used.

Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. This value must be different from 0.

In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional CRC. The PKTLEN register is used to set the maximum packet length allowed in RX. Any packet received with a length byte with a value greater than PKTLEN will be discarded. The PKTLEN value must be different from 0.

With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission and reception will continue until turned off manually. As described in Section 5.16.1.1, this can be used to support packet formats with different length configuration than natively supported by CC110L. One should make sure that TX mode is not turned off during the transmission of the first half of any byte. Refer to the CC110L Errata Notes SWRZ037 for more details.

NOTE

The minimum packet length supported (excluding the optional length byte and CRC) is one byte of payload data.

5.16.1.1 Arbitrary Length Field Configuration

The packet length register, PKTLEN, can be reprogrammed during receive and transmit. In combination with fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0), this opens the possibility to have a different length field configuration than supported for variable length packets (in variable packet length mode the length byte is the first byte after the sync word). At the start of reception, the packet length is set to a large value. The MCU reads out enough bytes to interpret the length field in the packet. Then the PKTLEN value is set according to this value. The end of packet will occur when the byte counter in the packet handler is equal to the PKTLEN register. Thus, the MCU must be able to program the correct length, before the internal counter reaches the packet length.

5.16.1.2 Packet Length > 255

The packet automation control register, PKTCTRL0, can be reprogrammed during TX and RX. This opens the possibility to transmit and receive packets that are longer than 256 bytes and still be able to use the packet handling hardware support. At the start of the packet, the infinite packet length mode (PKTCTRL0.LENGTH_CONFIG=2) must be active. On the TX side, the PKTLEN register is set to mod(length, 256). On the RX side the MCU reads out enough bytes to interpret the length field in the packet and sets the PKTLEN register to mod(length, 256). When less than 256 bytes remains of the packet, the MCU disables infinite packet length mode and activates fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0). When the internal byte counter reaches the PKTLEN value, the transmission or reception ends (the radio enters the state determined by TXOFF_MODE or RXOFF_MODE). Automatic CRC appending/checking can also be used (by setting PKTCTRL0.CRC_EN=1).

When for example a 600-byte packet is to be transmitted, the MCU should do the following (see Figure 5-7).

Set PKTCTRL0.LENGTH_CONFIG=2.
Pre-program the PKTLEN register to mod(600, 256) = 88.
Transmit at least 345 bytes (600 - 255), for example by filling the 64-byte TX FIFO six times (384 bytes transmitted).
Set PKTCTRL0.LENGTH_CONFIG=0.
The transmission ends when the packet counter reaches 88. A total of 600 bytes are transmitted.

Figure 5-7 Packet Length > 255

5.16.2 Packet Filtering in Receive Mode

CC110L supports three different types of packet-filtering; address filtering, maximum length filtering, and CRC filtering.

5.16.2.1 Address Filtering

Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter. The packet handler engine will compare the destination address byte in the packet with the programmed node address in the ADDR register and the 0x00 broadcast address when PKTCTRL1.ADR_CHK=10 or both the 0x00 and 0xFF broadcast addresses when PKTCTRL1.ADR_CHK=11. If the received address matches a valid address, the packet is received and written into the RX FIFO. If the address match fails, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting).

If the received address matches a valid address when using infinite packet length mode and address filtering is enabled, 0xFF will be written into the RX FIFO followed by the address byte and then the payload data.

5.16.2.2 Maximum Length Filtering

In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the PKTLEN.PACKET_LENGTH register value is used to set the maximum allowed packet length. If the received length byte has a larger value than this, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting).

5.16.2.3 CRC Filtering

The filtering of a packet when CRC check fails is enabled by setting PKTCTRL1.CRC_AUTOFLUSH=1. The CRC auto flush function will flush the entire RX FIFO if the CRC check fails. After auto flushing the RX FIFO, the next state depends on the MCSM1.RXOFF_MODE setting.

When using the auto flush function, the maximum packet length is 63 bytes in variable packet length mode and 64 bytes in fixed packet length mode. Note that when PKTCTRL1.APPEND_STATUS is enabled, the maximum allowed packet length is reduced by two bytes in order to make room in the RX FIFO for the two status bytes appended at the end of the packet. Since the entire RX FIFO is flushed when the CRC check fails, the previously received packet must be read out of the FIFO before receiving the current packet. The MCU must not read from the current packet until the CRC has been checked as OK.

5.16.3 Packet Handling in Transmit Mode

The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If address recognition is enabled on the receiver, the second byte written to the TX FIFO must be the address byte.

If fixed packet length is enabled, the first byte written to the TX FIFO should be the address (assuming the receiver uses address recognition).

The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word followed by the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO, and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has underflowed will not restart TX mode.

5.16.4 Packet Handling in Receive Mode

In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. When found, the demodulator has obtained both bit and byte synchronization and will receive the first payload byte. When variable packet length mode is enabled, the first byte is the length byte.

The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length mode is used, the packet handler will accept the programmed number of bytes.

Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appended CRC checksum.

At the end of the payload, the packet handler will optionally write two extra packet status bytes (see Table 5-5 and Table 5-6) that contain CRC status, link quality indication, and RSSI value.

5.16.5 Packet Handling in Firmware

When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been received/transmitted. Additionally, for packets longer than 64 bytes, the RX FIFO needs to be read while in RX and the TX FIFO needs to be refilled while in TX. This means that the MCU needs to know the number of bytes that can be read from or written to the RX FIFO and TX FIFO respectively. There are two possible solutions to get the necessary status information:

Interrupt Driven Solution

The GDO pins can be used in both RX and TX to give an interrupt when a sync word has been received/transmitted or when a complete packet has been received/transmitted by setting IOCFGx.GDOx_CFG=0x06. In addition, there are two configurations for the IOCFGx.GDOx_CFG register that can be used as an interrupt source to provide information on how many bytes that are in the RX FIFO and TX FIFO respectively. The IOCFGx.GDOx_CFG=0x00 and the IOCFGx.GDOx_CFG=0x01 configurations are associated with the RX FIFO while the IOCFGx.GDOx_CFG=0x02 and the IOCFGx.GDOx_CFG=0x03 configurations are associated with the TX FIFO. See Table 5-18 for more information.

SPI Polling

The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The RXBYTES and TXBYTES registers can be polled at a given rate to get information about the number of bytes in the RX FIFO and TX FIFO respectively. Alternatively, the number of bytes in the RX FIFO and TX FIFO can be read from the chip status byte returned on the MISO line each time a header byte, data byte, or command strobe is sent on the SPI bus.

It is recommended to employ an interrupt driven solution since high rate SPI polling reduces the RX sensitivity. Furthermore, as explained in Section 5.8 and the CC110L Errata Notes SWRZ037, when using SPI polling, there is a small, but finite, probability that a single read from registers PKTSTATUS , RXBYTES and TXBYTES is being corrupt. The same is the case when reading the chip status byte.

5.17 Modulation Formats

CC110L supports amplitude, frequency, and phase shift modulation formats. The desired modulation format is set in the MDMCFG2.MOD_FORMAT register.

Optionally, the data stream can be Manchester coded by the modulator and decoded by the demodulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN=1.

NOTE

Manchester encoding is not supported at the same time as using 4-FSK modulation.

5.17.1 Frequency Shift Keying

CC110L supports 2-(G)FSK and 4-FSK modulation. When selecting 4-FSK, the preamble and sync word to be received needs to be 2-FSK (see Figure 5-8).

When 2-FSK/GFSK/4-FSK modulation is used, the DEVIATN register specifies the expected frequency deviation of incoming signals in RX and should be the same as the deviation of the transmitted signal for demodulation to be performed reliably and robustly.

The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by:

Equation 5. CC110L equat_6_swrs109.gif

The symbol encoding is shown in Table 5-7.

Table 5-7 Symbol Encoding for 2-FSK/GFSK and 4-FSK Modulation

Format	Symbol	Coding
2-FSK/GFSK	0	– Deviation
2-FSK/GFSK	1	+ Deviation
4-FSK	01	– Deviation
	00	– 1/3×Deviation
	10	+ 1/3×Deviation
	11	+ Deviation

Figure 5-8 Data Sent Over the Air (MDMCFG2.MOD_FORMAT=100)

5.17.2 Amplitude Modulation

The amplitude modulation supported by CC110L is On-Off Keying (OOK).

OOK modulation simply turns the PA on or off to modulate ones and zeros respectively.

When using OOK, the AGC settings from the SmartRF Studio SWRC176 preferred FSK settings are not optimum. DN022 SWRA215 gives guidelines on how to find optimum OOK settings from the preferred settings in SmartRF Studio SWRC176. The DEVIATN register setting has no effect in either TX or RX when using OOK.

5.18 Received Signal Qualifiers and RSSI

CC110L has several qualifiers that can be used to increase the likelihood that a valid sync word is detected:

Sync Word Qualifier
RSSI
Carrier Sense
Clear Channel Assessment

5.18.1 Sync Word Qualifier

If sync word detection in RX is enabled in the MDMCFG2 register, the CC110L will not start filling the RX FIFO and perform the packet filtering described in Section 5.16.2 before a valid sync word has been detected. The sync word qualifier mode is set by MDMCFG2.SYNC_MODE and is summarized in Table 5-8. Carrier sense described in Section 5.18.3.

Table 5-8 Sync Word Qualifier Mode

MDMCFG2.SYNC_MODE	Sync Word Qualifier Mode
000	No preamble/sync
001	15/16 sync word bits detected
010	16/16 sync word bits detected
011	30/32 sync word bits detected
100	No preamble/sync + carrier sense above threshold
101	15/16 + carrier sense above threshold
110	16/16 + carrier sense above threshold
111	30/32 + carrier sense above threshold

5.18.2 RSSI

The RSSI value is an estimate of the signal power level in the chosen channel. This value is based on the current gain setting in the RX chain and the measured signal level in the channel.

In RX mode, the RSSI value can be read continuously from the RSSI status register until the demodulator detects a sync word (when sync word detection is enabled). At that point the RSSI readout value is frozen until the next time the chip enters the RX state.

NOTE

It takes some time from the radio enters RX mode until a valid RSSI value is present in the RSSI register. See DN505 SWRA114 for details on how the RSSI response time can be estimated.

The RSSI value is given in dBm with a ½-dB resolution. The RSSI update rate, f_RSSI, depends on the receiver filter bandwidth (BW_channel is defined in Section 5.14) and AGCCTRL0.FILTER_LENGTH.

Equation 6. CC110L equat_7_swrs109.gif

If PKTCTRL1.APPEND_STATUS is enabled, the last RSSI value of the packet is automatically added to the first byte appended after the payload.

The RSSI value read from the RSSI status register is a 2s complement number. The following procedure can be used to convert the RSSI reading to an absolute power level (RSSI_dBm).

Read the RSSI status register
Convert the reading from a hexadecimal number to a decimal number (RSSI_dec)
If RSSI_dec ≥ 128 then RSSI_dBm = (RSSI_dec - 256)/2 – RSSI_offset
Else if RSSI_dec < 128 then RSSI_dBm = (RSSI_dec)/2 – RSSI_offset

Table 5-9 gives typical values for the RSSI_offset. Figure 5-9 and Figure 5-10 show typical plots of RSSI readings as a function of input power level for different data rates.

Table 5-9 Typical RSSI_offset Values

Data rate [kBaud]	RSSI_offset [dB], 433 MHz	RSSI_offset [dB], 868 MHz
1.2	74	74
38.4	74	74
250	74	74

spacer

Figure 5-9 Typical RSSI Value Versus Input Power Level for Different Data Rates at 433 MHz

Figure 5-10 Typical RSSI Value Versus Input Power Level for Different Data Rates at 868 MHz

5.18.3 Carrier Sense (CS)

Carrier sense (CS) is used as a sync word qualifier and for Clear Channel Assessment (see Section 5.18.4). CS can be asserted based on two conditions which can be individually adjusted:

CS is asserted when the RSSI is above a programmable absolute threshold, and deasserted when RSSI is below the same threshold (with hysteresis). See more in Section 5.18.3.1.
CS is asserted when the RSSI has increased with a programmable number of dB from one RSSI sample to the next, and deasserted when RSSI has decreased with the same number of dB. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with time varying noise floor. See more in Section 5.18.3.2.

Carrier sense can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed and is set by setting MDMCFG2 The carrier sense signal can be observed on one of the GDO pins by setting IOCFGx.GDOx_CFG=14 and in the status register bit PKTSTATUS.CS.

Other uses of Carrier sense include the TX-if-CCA function (see Section 5.18.4) and the optional fast RX termination (see Section 5.19.5). CS can be used to avoid interference from other RF sources in the ISM bands.

5.18.3.1 CS Absolute Threshold

The absolute threshold related to the RSSI value depends on the following register fields:

AGCCTRL2.MAX_LNA_GAIN
AGCCTRL2.MAX_DVGA_GAIN
AGCCTRL1.CARRIER_SENSE_ABS_THR
AGCCTRL2.MAGN_TARGET

For given AGCCTRL2.MAX_LNA_GAIN and AGCCTRL2.MAX_DVGA_GAIN settings, the absolute threshold can be adjusted ±7 dB in steps of 1 dB using CARRIER_SENSE_ABS_THR.

The MAGN_TARGET setting is a compromise between blocker tolerance/selectivity and sensitivity. The value sets the desired signal level in the channel into the demodulator. Increasing this value reduces the headroom for blockers, and therefore close-in selectivity. It is strongly recommended to use SmartRF Studio SWRC176 to generate the correct MAGN_TARGET setting. Table 5-10 shows the typical RSSI readout values at the CS threshold at 250 kBaud data rate. The default reset value for CARRIER_SENSE_ABS_THR (0 dB) has been used. MAGN_TARGET=111 (42 dB) have been used for the 250 kBaud data rate. For other data rates, the user must generate similar tables to find the CS absolute threshold.

Table 5-10 Typical RSSI Value in dBm at CS Threshold with MAGN_TARGET = 7 (42 dB) at 250 kBaud, 868 MHz

		MAX_DVGA_GAIN[1:0]
		00	01	10	11
MAX_LNA_GAIN[2:0]	000	−90.5	−84.5	−78.5	−72.5
	001	−88	−82	−76	−70
	010	−84.5	−78.5	−72	−66
	011	−82.5	−76.5	−70	−64
	100	−80.5	−74.5	−68	−62
	101	−78	−72	−66	−60
	110	−76.5	−70	−64	−58
	111	−74.5	−68	−62	−56

If the threshold is set high, that is, only strong signals are wanted, the threshold should be adjusted upwards by first reducing the MAX_LNA_GAIN value and then the MAX_DVGA_GAIN value. This will reduce power consumption in the receiver front end, since the highest gain settings are avoided.

5.18.3.2 CS Relative Threshold

The relative threshold detects sudden changes in the measured signal level. This setting does not depend on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. The register field AGCCTRL1.CARRIER_SENSE_REL_THR is used to enable/disable relative CS, and to select threshold of 6 dB, 10 dB, or 14 dB RSSI change.

5.18.4 Clear Channel Assessment (CCA)

The Clear Channel Assessment (CCA) is used to indicate if the current channel is free or busy. The current CCA state is viewable on any of the GDO pins by setting IOCFGx.GDOx_CFG=0x09.

MCSM1.CCA_MODE selects the mode to use when determining CCA.

When the STX or SFSTXON command strobe is given while CC110L is in the RX state, the TX or FSTXON state is only entered if the clear channel requirements are fulfilled. Otherwise, the chip will remain in RX. If the channel then becomes available, the radio will not enter TX or FSTXON state before a new strobe command is sent on the SPI interface. This feature is called TX-if-CCA. Four CCA requirements can be programmed:

Always (CCA disabled, always goes to TX)
If RSSI is below threshold
Unless currently receiving a packet
Both the above (RSSI below threshold and not currently receiving a packet)

5.19 Radio Control

CC110L complete_radio_control_state_diagram_swrs109.gif

Figure 5-11 Complete Radio Control State Diagram

CC110L has a built-in state machine that is used to switch between different operational states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow.

A simplified state diagram, together with typical usage and current consumption, is shown in Figure 5-2. The complete radio control state diagram is shown in Figure 5-11. The numbers refer to the state number readable in the MARCSTATE status register. This register is primarily for test purposes.

5.19.1 Power-On Start-Up Sequence

When the power supply is turned on, the system must be reset. This is achieved by one of the two sequences described below, that is, automatic power-on reset (POR) or manual reset. After the automatic power-on reset or manual reset, it is also recommended to change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192. However, to optimize performance in TX and RX, an alternative GDO setting from the settings found in Table 5-18 should be selected.

5.19.1.1 Automatic POR

A power-on reset circuit is included in the CC110L. The minimum requirements stated in Section 4.12 must be followed for the power-on reset to function properly. The internal power-up sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section 5.6 for more details on CHIP_RDYn. When the CC110L reset is completed, the chip will be in the IDLE state and the crystal oscillator will be running. If the chip has had sufficient time for the crystal oscillator to stabilize after the power-on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed, the SO pin will first go high, indicating that the crystal oscillator is not stabilized, before going low as shown in Figure 5-12.

Figure 5-12 Power-On Reset with SRES

5.19.1.2 Manual Reset

The other global reset possibility on CC110L uses the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The manual power-up sequence is as follows (see Figure 5-13):

Set SCLK = 1 and SI = 0.
Strobe CSn low / high.
Hold CSn low and then high for at least 40 µs relative to pulling CSn low
Pull CSn low and wait for SO to go low (CHIP_RDYn).
Issue the SRES strobe on the SI line.
When SO goes low again, reset is complete and the chip is in the IDLE state.

XOSC and voltage regulator switched on

CC110L power_on_reset_with_SRES_swrs109.gif

Figure 5-13 Power-On Reset with SRES

NOTE

The above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the CC110L after this, it is only necessary to issue an SRES command strobe.

5.19.2 Crystal Control

The crystal oscillator (XOSC) is either automatically controlled or always on, if MCSM0.XOSC_FORCE_ON is set.

In the automatic mode, the XOSC will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can only be done from the IDLE state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the IDLE state. The SO pin on the SPI interface must be pulled low before the SPI interface is ready to be used as described in Section 5.6.

If the XOSC is forced on, the crystal will always stay on even in the SLEEP state.

Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification for the crystal oscillator can be found in Section 4.9.

5.19.3 Voltage Regulator Control

The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is then in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state.

5.19.4 Active Modes (RX and TX)

CC110L has two active modes: receive and transmit. These modes are activated directly by the MCU by using the SRX and STX command strobes.

The frequency synthesizer must be calibrated regularly. CC110L has one manual calibration option (using the SCAL strobe), and three automatic calibration options that are controlled by the MCSM0.FS_AUTOCAL setting:

Calibrate when going from IDLE to either RX or TX (or FSTXON)
Calibrate when going from either RX or TX to IDLE automatically (not forced in IDLE by issuing an SIDLE strobe)
Calibrate every fourth time when going from either RX or TX to IDLE automatically (not forced in IDLE by issuing an SIDLE strobe)
RX: Start search for a new packet

NOTE

When MCSM1.RXOFF_MODE=11 and a packet has been received, it will take some time before a valid RSSI value is present in the RSSI register again even if the radio has never exited RX mode. This time is the same as the RSSI response time discussed in DN505 SWRA114.

Similarly, when TX is active the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are the same as for RX.

The MCU can manually change the state from RX to TX and vice versa by using the command strobes. If the radio controller is currently in transmit and the SRX strobe is used, the current transmission will be ended and the transition to RX will be done.

If the radio controller is in RX when the STX or SFSTXON command strobes are used, the TX- if-CCA function will be used. If the channel is not clear, the chip will remain in RX. The MCSM1.CCA_MODE setting controls the conditions for clear channel assessment. See Section 5.18.4.

The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state.

5.19.5 RX Termination

If the system expects the transmission to have started when entering RX mode, the MCSM2.RX_TIME_RSSI function can be used. The radio controller will then terminate RX if the first valid carrier sense sample indicates no carrier (RSSI below threshold). See Section 5.18.3 for details on Carrier Sense.

For OOK modulation, lack of carrier sense is only considered valid after eight symbol periods. Thus, the MCSM2.RX_TIME_RSSI function can be used in OOK mode when the distance between two “1” symbols is eight or less.

5.19.6 Timing

5.19.6.1 Overall State Transition Times

The main radio controller needs to wait in certain states in order to make sure that the internal analog/digital parts have settled down and are ready to operate in the new states. A number of factors are important for the state transition times:

The crystal oscillator frequency, f_xosc
OOK used or not
The data rate in cases where OOK is used
The value of the TEST0, TEST1, and FSCAL3 registers

Table 5-11 shows timing in crystal clock cycles for key state transitions.

Note that the TX to IDLE transition time is a function of data rate (fbaudrate). When OOK is used (that is, FREND0.PA_POWER=001b), TX to IDLE will require 1/8×f baudrate longer times than the time stated in Table 5-11.

Table 5-11 Overall State Transition Times [Example for 26-MHz Crystal Oscillator, 250 kBaud Data Rate, and TEST0 = 0x0B (Maximum Calibration Time)].

Description	Transition Time (FREND0.PA_POWER=0)	Transition Time [µs]
IDLE to RX, no calibration	1953/f_xosc	75.1
IDLE to RX, with calibration	1953/_fxosc + FS calibration Time	799
IDLE to TX/FSTXON, no calibration	1954/f_xosc	75.2
IDLE to TX/FSTXON, with calibration	1953/f_xosc + FS calibration Time	799
TX to RX switch	782/f_xosc + 0.25/f_baudrate	31.1
RX to TX switch	782/f_xosc	30.1
TX to IDLE, no calibration	~0.25/f_baudrate	~1
TX to IDLE, with calibration	~0.25/f_baudrate + FS calibration Time	725
RX to IDLE, no calibration	2/f_xosc	~0.1
RX to IDLE, with calibration	2/f_xosc + FS calibration Time	724
Manual calibration	283/f_xosc + FS calibration Time	735

5.19.6.2 Frequency Synthesizer Calibration Time

Table 5-12 summarizes the frequency synthesizer (FS) calibration times for possible settings of TEST0 and FSCAL3.CHP_CURR_CAL_EN. Setting FSCAL3.CHP_CURR_CAL_EN to 00b disables the charge pump calibration stage. TEST0 is set to the values recommended by SmartRF Studio software . The possible values for TEST0 when operating with different frequency bands are 0x09 and 0x0B. SmartRF Studio software always sets FSCAL3.CHP_CURR_CAL_EN to 10b.

The calibration time can be reduced from 712/724 µs to 145/157 µs. See Section 5.27.2 for more details.

Table 5-12 Frequency Synthesizer Calibration Times (26- and 27-MHz Crystal)

TEST0	FSCAL3.CHP_CURR_CAL_EN	FS Calibration Time f_xosc = 26 MHz	FS Calibration Time f_xosc = 27 MHz
0x09	00b	3764/f_xosc = 145 µs	3764/f_xosc = 139 µs
0x09	10b	18506/f_xosc= 712 µs	18506/f_xosc = 685 µs
0x0B	00b	4073/f_xosc = 157 µs	4073/f_xosc = 151 µs
0x0B	10b	18815/f_xosc = 724 µs	18815/f_xosc = 697 µs

5.20 Data FIFO

The CC110L contains two 64-byte FIFOs, one for received data and one for data to be transmitted. The SPI interface is used to read from the RX FIFO and write to the TX FIFO. Section 5.10 contains details on the SPI FIFO access. The FIFO controller will detect overflow in the RX FIFO and underflow in the TX FIFO.

When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO overflow will result in an error in the TX FIFO content.

Likewise, when reading the RX FIFO the MCU must avoid reading the RX FIFO past its empty value since a RX FIFO underflow will result in an error in the data read out of the RX FIFO.

The chip status byte that is available on the SO pin while transferring the SPI header and contains the fill grade of the RX FIFO if the access is a read operation and the fill grade of the TX FIFO if the access is a write operation. Section 5.6 contains more details on this.

The number of bytes in the RX FIFO and TX FIFO can be read from the status registers RXBYTES.NUM_RXBYTES and TXBYTES.NUM_TXBYTES respectively. If a received data byte is written to the RX FIFO at the exact same time as the last byte in the RX FIFO is read over the SPI interface, the RX FIFO pointer is not properly updated and the last read byte will be duplicated. To avoid this problem, the RX FIFO should never be emptied before the last byte of the packet is received.

For packet lengths less than 64 bytes it is recommended to wait until the complete packet has been received before reading it out of the RX FIFO.

If the packet length is larger than 64 bytes, the MCU must determine how many bytes can be read from the RX FIFO (RXBYTES.NUM_RXBYTES-1). The following software routine can be used:

Read RXBYTES.NUM_RXBYTES repeatedly at a rate specified to be at least twice that of which RF bytes are received until the same value is returned twice; store value in n.
If n < # of bytes remaining in packet, read n-1 bytes from the RX FIFO.
Repeat steps 1 and 2 until n = number of bytes remaining in packet.
Read the remaining bytes from the RX FIFO.

The 4-bit FIFOTHR.FIFO_THR setting is used to program threshold points in the FIFOs.

Table 5-13 lists the 16 FIFO_THR settings and the corresponding thresholds for the RX and TX FIFOs. The threshold value is coded in opposite directions for the RX FIFO and TX FIFO. This gives equal margin to the overflow and underflow conditions when the threshold is reached.

Table 5-13 FIFO_THR Settings and the Corresponding FIFO Thresholds

FIFO_THR	Bytes in TX FIFO	Bytes in RX FIFO
0 (0000)	61	4
1 (0001)	57	8
2 (0010)	53	12
3 (0011)	49	16
4 (0100)	45	20
5 (0101)	41	24
6 (0110)	37	28
7 (0111)	33	32
8 (1000)	29	36
9 (1001)	25	40
10 (1010)	21	44
11 (1011)	17	48
12 (1100)	13	52
13 (1101)	9	56
14 (1110)	5	60
15 (1111)	1	64

A signal will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold. This signal can be viewed on the GDO pins (see Table 5-18).

Figure 5-14 shows the number of bytes in both the RX FIFO and TX FIFO when the threshold signal toggles in the case of FIFO_THR=13. Figure 5-15 shows the signal on the GDO pin as the respective FIFO is filled above the threshold, and then drained below in the case of FIFO_THR=13.

CC110L examples_of_FIFOs_at_threshold_swrs109.gif

Figure 5-14 Example of FIFOs at Threshold

Figure 5-15 Number of Bytes in FIFO versus the GDO Signal (GDOx_CFG=0x00 in RX and GDOx_CFG=0x02 in TX, FIFO_THR=13)

5.21 Frequency Programming

The frequency programming in CC110L is designed to minimize the programming needed when changing frequency.

To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively. The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1, and FREQ0 registers. This word will typically be set to the center of the lowest channel frequency that is to be used.

The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, which is multiplied by the channel offset. The resultant carrier frequency is given by:

Equation 7. CC110L equat_8_swrs109.gif

With a 26 MHz crystal the maximum channel spacing is 405 kHz. To get that is, 1-MHz channel spacing, one solution is to use 333 kHz channel spacing and select each third channel in CHANNR.CHAN.

The preferred IF frequency is programmed with the FSCTRL1.FREQ_IF register. The IF frequency is given by:

Equation 8. CC110L equat_9_swrs109.gif

If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency should only be updated when the radio is in the IDLE state.

5.22 VCO

The VCO is completely integrated on-chip.

5.22.1 VCO and PLL Self-Calibration

The VCO characteristics vary with temperature and supply voltage changes as well as the desired operating frequency. In order to ensure reliable operation, CC110L includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLL calibration is given in Table 5-11.

The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE mode.

NOTE

The calibration values are maintained in SLEEP mode, so the calibration is still valid after waking up from SLEEP mode unless supply voltage or temperature has changed significantly.

To check that the PLL is in lock, the user can program register IOCFGx.GDOx_CFG to 0x0A, and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0,1, or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. Refer also to the CC110L Errata Notes SWRZ037.

For more robust operation, the source code could include a check so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock the first time.

5.23 Voltage Regulators

CC110L contains several on-chip linear voltage regulators that generate the supply voltages needed by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and required pin voltages in Table 3-1 and Table 5-1 are not exceeded.

By setting the CSn pin low, the voltage regulator to the digital core turns on and the crystal oscillator starts. The SO pin on the SPI interface must go low before the first positive edge of SCLK (setup time is given in Table 5-1).

If the chip is programmed to enter power-down mode (SPWD strobe issued), the power will be turned off after CSn goes high. The power and crystal oscillator will be turned on again when CSn goes low.

The voltage regulator for the digital core requires one external decoupling capacitor.

The voltage regulator output should only be used for driving the CC110L.

5.24 Output Power Programming

The RF output power level from the device has two levels of programmability. The PATABLE register can hold two user selected output power settings and the FREND0.PA_POWER value selects the PATABLE entry to use (0 or 1). PATABLE must be programmed in burst mode if writing to other entries than PATABLE[0]. See Section 5.11 for more programming details.

For OOK modulation, FREND0.PA_POWER should be 1 and the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively. For all other modulation formats, the desired output power should be programmed to index 0.

Table 5-14 contains the recommended PATABLE settings for various output levels and frequency bands. DN013 SWRA168 gives the complete tables for the different frequency bands using multi-layer inductors. Using PA settings from 0x61 to 0x6F is not allowed. Table 5-17 contains output power and current consumption for default PATABLE setting (0xC6). The measurements are done on SWRR045.

NOTE

All content of the PATABLE except for the first byte (index 0) is lost when entering the SLEEP state.

Table 5-14 Optimum PATABLE Settings for Various Output Power Levels Using Wire-Wound Inductors in 868- and 915-MHz Frequency Bands

	868 MHz		915 MHz
Output Power [dBm]	Setting	Current Consumption, Typ. [mA]	Setting	Current Consumption, Typ. [mA]
12/11	0xC0	34.2	0xC0	33.4
10	0xC5	30.0	0xC3	30.7
7	0xCD	25.8	0xCC	25.7
5	0x86	19.9	0x84	20.2
0	0x50	16.8	0x8E	17.2
−6	0x37	16.4	0x38	17.0
−10	0x26	14.5	0x27	14.8
−15	0x1D	13.3	0x1E	13.3
−20	0x17	12.6	0x0E	12.5
−30	0x03	12.0	0x03	11.9

Table 5-15 Output Power and Current Consumption for Default PATABLE Setting Using Wire-Wound Inductors in 868- and 915-MHz Frequency Bands

	868 MHz		915 MHz
Default Power Setting	Output Power [dBm]	Current Consumption, Typ. [mA]	Output Power [dBm]	Current Consumption, Typ. [mA]
0xC6	9.6	29.4	8.9	28.7

Table 5-16 Optimum PATABLE Settings for Various Output Power Levels Using Multi-layer Inductors in 868- and 915-MHz Frequency Bands

	868 MHz		915 MHz
Output Power [dBm]	Setting	Current Consumption, Typ. [mA]	Setting	Current Consumption, Typ. [mA]
10	0xC2	32.4	0xC0	31.8
7	0xCB	26.8	0xC7	26.9
5	0x81	21.0	0xCD	24.3
0	0x50	16.9	0x8E	16.7
−10	0x27	15.0	0x27	14.9
−15	0x1E	13.4	0x1E	13.4
−20	0x0F	12.7	0x0E	12.6
−30	0x03	12.1	0x03	12.0

Table 5-17 Output Power and Current Consumption for Default PATABLE Setting Using Multi-layer Inductors in 868- and 915-MHz Frequency Bands

	868 MHz		915 MHz
Default Power Setting	Current Consumption, Typ. [mA]	Output Power [dBm]	Current Consumption, Typ. [mA]	Output Power [dBm]
0xC6	8.5	29.5	7.2	27.4

5.25 General Purpose and Test Output Control Pins

The three digital output pins GDO0, GDO1, and GDO2 are general control pins configured with IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG respectively. Table 5-18 shows the different signals that can be monitored on the GDO pins. These signals can be used as inputs to the MCU.

GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin will only be valid when CSn is high. The default value for GDO1 is 3-stated which is useful when the SPI interface is shared with other devices.

The default value for GDO0 is a 135-141 kHz clock output (XOSC frequency divided by 192). Since the XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one crystal. When the MCU is up and running, it can change the clock frequency by writing to IOCFG0.GDO0_CFG.

If the IOCFGx.GDOx_CFG setting is less than 0x20 and IOCFGx_GDOx_INV is 0 (1), the GDO0 and GDO2 pins will be hardwired to 0 (1), and the GDO1 pin will be hardwired to 1 (0) in the SLEEP state. These signals will be hardwired until the CHIP_RDYn signal goes low.

If the IOCFGx.GDOx_CFG setting is 0x20 or higher, the GDO pins will work as programmed also in SLEEP state. As an example, GDO1 is high impedance in all states if IOCFG1.GDO1_CFG=0x2E.

Table 5-18 GDOx Signal Selection (x = 0, 1, or 2)

GDOx_CFG[5:0]	Description⁽¹⁾
0 (0x00)	Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. Deasserts when RX FIFO is drained below the same threshold.
1 (0x01)	Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is reached. Deasserts when the RX FIFO is empty.
2 (0x02)	Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. Deasserts when the TX FIFO is below the same threshold.
3 (0x03)	Associated to the TX FIFO: Asserts when TX FIFO is full. Deasserts when the TX FIFO is drained below the TX FIFO threshold.
4 (0x04)	Asserts when the RX FIFO has overflowed. Deasserts when the FIFO has been flushed.
5 (0x05)	Asserts when the TX FIFO has underflowed. Deasserts when the FIFO is flushed.
6 (0x06)	Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will also de-assert when a packet is discarded due to address or maximum length filtering or when the radio enters RXFIFO_OVERFLOW state. In TX the pin will de-assert if the TX FIFO underflows.
7 (0x07)	Asserts when a packet has been received with CRC OK. Deasserts when the first byte is read from the RX FIFO.
8 (0x08)	Reserved - used for test.
9 (0x09)	Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting).
10 (0x0A)	Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To check for PLL lock the lock detector output should be used as an interrupt for the MCU.
11 (0x0B)	Serial Clock. Synchronous to the data in synchronous serial mode. In RX mode, data is set up on the falling edge by CC110L when GDOx_INV=0. In TX mode, data is sampled by CC110L on the rising edge of the serial clock when GDOx_INV=0.
12 (0x0C)	Serial Synchronous Data Output. Used for synchronous serial mode.
13 (0x0D)	Serial Data Output. Used for asynchronous serial mode.
14 (0x0E)	Carrier sense. High if RSSI level is above threshold. Cleared when entering IDLE mode.
15 (0x0F)	CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode.
16 (0x10) – 26 (0x1A)	Reserved - used for test.
27 (0x1B)	PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA or RX/TX switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.
28 (0x1C)	LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an external LNA or RX/TX switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.
29 (0x1D) – 38 (0x26)	Reserved - used for test.
39 (0x27)	CLK_32k.
40 (0x28)	Reserved - used for test.
41 (0x29)	CHIP_RDYn.
42 (0x2A)	Reserved - used for test.
43 (0x2B)	XOSC_STABLE.
44 (0x2C) - 45 (0x2D)	Reserved - used for test.
46 (0x2E)	High impedance (3-state).
47 (0x2F)	HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA/PA or RX/TX switch.
48 (0x30)	CLK_XOSC/1	Note: There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other two GDO pins must be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192. To optimize RF performance, these signals should not be used while the radio is in RX mode.
49 (0x31)	CLK_XOSC/1.5
50 (0x32)	CLK_XOSC/2
51 (0x33)	CLK_XOSC/3
52 (0x34)	CLK_XOSC/4
53 (0x35)	CLK_XOSC/6
54 (0x36)	CLK_XOSC/8
55 (0x37)	CLK_XOSC/12
56 (0x38)	CLK_XOSC/16
57 (0x39)	CLK_XOSC/24
58 (0x3A)	CLK_XOSC/32
59 (0x3B)	CLK_XOSC/48
60 (0x3C)	CLK_XOSC/64
61 (0x3D)	CLK_XOSC/96
62 (0x3E)	CLK_XOSC/128
63 (0x3F)	CLK_XOSC/192

(1) There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other two GDO pins must be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.
To optimize RF performance, these signals should not be used while the radio is in RX or TX mode.

5.26 Asynchronous and Synchronous Serial Operation

Several features and modes of operation have been included in the CC110L to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication, significantly offload the microcontroller, and simplify software development.

5.26.1 Asynchronous Serial Operation

Asynchronous transfer is included in the CC110L for backward compatibility with systems that are already using the asynchronous data transfer.

When asynchronous transfer is enabled, all packet handling support is disabled and it is not possible to use Manchester encoding.

Asynchronous serial mode is enabled by setting PKTCTRL0.PKT_FORMAT to 3. Strobing STX will configure the GDO0 pin as data input (TX data) regardless of the content of the IOCFG0 register. Data output can be on GDO0, GDO1, or GDO2. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG fields.

The CC110L modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate.

In asynchronous serial mode no data decision is done on-chip and the raw data is put on the data output line. When using asynchronous serial mode make sure the interfacing MCU does proper oversampling and that it can handle the jitter on the data output line. The MCU should tolerate a jitter of ±1/8 of a bit period as the data stream is time-discrete using 8 samples per bit.

In asynchronous serial mode there will be glitches of 37 - 38.5 ns duration (1/XOSC) occurring infrequently and with random periods. A simple RC filter can be added to the data output line between CC110L and the MCU to get rid of the 37 - 38.5 ns glitches if considered a problem. The filter 3 dB cut-off frequency needs to be high enough so that the data is not filtered and at the same time low enough to remove the glitch. As an example, for 2.4 kBaud data rate a 1 kΩ resistor and 2.7 nF capacitor can be used. This gives a 3 dB cut-off frequency of 59 kHz.

5.26.2 Synchronous Serial Operation

Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. When using this mode, sync detection should be disabled together with CRC calculation (MDMCFG2.SYNC_MODE=000 and PKTCTRL0.CRC_EN=0). Infinite packet length mode should be used (PKTCTRL0.LENGTH_CONFIG=10b).

In synchronous serial mode, data is transferred on a two-wire serial interface. The CC110L provides a clock that is used to set up new data on the data input line or sample data on the data output line. Data input (TX data) is on the GDO0 pin. This pin will automatically be configured as an input when TX is active. The TX latency is 8 bits. The data output pin can be any of the GDO pins. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG fields. The RX latency is 9 bits.

The MCU must handle preamble and sync word detection in software.

The MCU must handle preamble and sync word insertion/detection in software, together with CRC calculation and insertion.

5.27 System Considerations and Guidelines

5.27.1 SRD Regulations

International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315 MHz, 433 MHz, 868 MHz or 915 MHz frequency bands. The CC110L is specifically designed for such use with its 300 - 348 MHz, 387 - 464 MHz, and 779 - 928 MHz operating ranges. The most important regulations when using the CC110L in the 315 MHz, 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220 V2.3.1 (Europe) and FCC CFR47 Part 15 (USA).

For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz.

Compliance with regulations is dependent on the complete system performance. It is the customer's responsibility to ensure that the system complies with regulations.

5.27.2 Frequency Hopping and Multi-Channel Systems

CC110L is highly suited for FHSS or multi- channel systems due to its agile frequency synthesizer and effective communication interface.

Charge pump current, VCO current, and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for CC110L. There are 3 ways of obtaining the calibration data from the chip:

Frequency hopping with calibration for each hop. The PLL calibration time is 712/724 µs (26 MHz crystal and TEST0 = 0x09/0B, see Table 5-12). The blanking interval between each frequency hop is then 787/799 µs.
Fast frequency hopping without calibration for each hop can be done by performing the necessary calibrating at startup and saving the resulting FSCAL3, FSCAL2, and FSCAL1 register values in MCU memory. The VCO capacitance calibration FSCAL1 register value must be found for each RF frequency to be used. The VCO current calibration value and the charge pump current calibration value available in FSCAL2 and FSCAL3 respectively are not dependent on the RF frequency, so the same value can therefore be used for all RF frequencies for these two registers. Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values that corresponds to the next RF frequency. The PLL turn on time is approximately 75 µs (see Table 5-11). The blanking interval between each frequency hop is then approximately 75 µs.
Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4], strobe SRX (or STX) with MCSM0.FS_AUTOCAL=1 for each new frequency hop. That is, VCO current and VCO capacitance calibration is done, but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from 712/724 µs to 145/157 µs (26 MHz crystal and TEST0 = 0x09/0B, see Table 5-12). The blanking interval between each frequency hop is then 220/232 µs.

There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. This solution also requires that the supply voltage and temperature do not vary much in order to have a robust solution. Solution 3) gives 567 µs smaller blanking interval than solution 1).

The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. This means that one should always use SmartRF Studio to get the correct settings for a specific frequency before doing a calibration, regardless of which calibration method is being used.

NOTE

The content in the TEST0 register is not retained in SLEEP state, thus it is necessary to re-write this register when returning from the SLEEP state.

5.27.3 Wideband Modulation when not Using Spread Spectrum

Digital modulation systems under FCC Section 15.247 include 2-FSK, GFSK, and 4-FSK modulation. A maximum peak output power of 1 W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in any 3 kHz band.

Operating at high data rates and frequency separation, the CC110L is suited for systems targeting compliance with digital modulation system as defined by FCC Section 15.247. An external power amplifier such as CC1190 SWRS089 is needed to increase the output above +11 dBm. Refer to DN006 SWRA123 for further details concerning wideband modulation and CC110L.

5.27.4 Data Burst Transmissions

The high maximum data rate of CC110L opens up for burst transmissions. A low average data rate link (that is, 10 kBaud) can be realized by using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (that is, 500 kBaud) will reduce the time in active mode, and hence also reduce the average current consumption significantly.

Reducing the time in active mode will reduce the likelihood of collisions with other systems in the same frequency range.

NOTE

The sensitivity and thus transmission range is reduced for high data rate bursts compared to lower data rates.

5.27.5 Continuous Transmissions

In data streaming applications, the CC110L opens up for continuous transmissions at 500 kBaud effective data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a transmission (open loop modulation used in some transceivers often prevents this kind of continuous data streaming and reduces the effective data rate).

5.27.6 Increasing Range

In some applications it may be necessary to extend the range. The CC1190 SWRS089 is a range extender for 850-950 MHz RF transceivers, transmitters, and System-on-Chip devices from Texas Instruments. It increases the link budget by providing a power amplifier (PA) for increased output power, and a low-noise amplifier (LNA) with low noise figure for improved receiver sensitivity in addition to switches and RF matching for simple design of high performance wireless systems. Refer to AN094 SWRA356 and AN096 SWRA361 for performance figures of the CC110L and CC1190 combination. Figure 5-16 shows a simplified application circuit.

CC110L simplified_CC110L_CC1190_app_swrs109.gif

Figure 5-16 Simplified CC110L-CC1190 Application Circuit

5.28 Configuration Registers

The configuration of CC110L is done by programming 8-bit registers. The optimum configuration data based on selected system parameters are most easily found by using the SmartRF Studio software . Complete descriptions of the registers are given in the following tables. After chip reset, all the registers have default values as shown in the tables. The optimum register setting might differ from the default value. After a reset, all registers that shall be different from the default value therefore needs to be programmed through the SPI interface.

There are 11 command strobe registers, listed in Table 5-19. Accessing these registers will initiate the change of an internal state or mode. There are 44 normal 8-bit configuration registers listed in Table 5-20 and SmartRF Studio will provide recommended settings for these registers (Addresses marked as “Not Used” can be part of a burst access and one can write a dummy value to them. Addresses marked as “Reserved” must be configured according to SmartRF Studio ).

There are also 9 status registers that are listed in Table 5-21. These registers, which are read- only, contain information about the status of CC110L.

The two FIFOs are accessed through one 8-bit register. Write operations write to the TX FIFO, while read operations read from the RX FIFO.

During the header byte transfer and while writing data to a register or the TX FIFO, a status byte is returned on the SO line. This status byte is described in Table 5-2.

Table 5-22 summarizes the SPI address space. The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for base addresses above and below 0x2F.

Table 5-19 Command Strobes

Address	Strobe Name	Description
0x30	SRES	Reset chip.
0x31	SFSTXON	Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA): Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
0x32	SXOFF	Turn off crystal oscillator.
0x33	SCAL	Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (MCSM0.FS_AUTOCAL=0)
0x34	SRX	In IDLE state: Enable RX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
0x35	STX	In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: Only go to TX if channel is clear.
0x36	SIDLE	Enter IDLE state
0x37 - 0x38	Reserved
0x39	SPWD	Enter power down mode when CSn goes high.
0x3A	SFRX	Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states.
0x3B	SFTX	Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states.
0x3C	Reserved
0x3D	SNOP	No operation. May be used to get access to the chip status byte.

Table 5-20 Configuration Registers Overview

Address	Register	Description	Preserved in SLEEP State	Details on Page Number
0x00	IOCFG2	GDO2 output pin configuration	Yes	Table 5-23
0x01	IOCFG1	GDO1 output pin configuration	Yes	Table 5-24
0x02	IOCFG0	GDO0 output pin configuration	Yes	Table 5-25
0x03	FIFOTHR	RX FIFO and TX FIFO thresholds	Yes	Table 5-26
0x04	SYNC1	Sync word, high byte	Yes	Table 5-27
0x05	SYNC0	Sync word, low byte	Yes	Table 5-28
0x06	PKTLEN	Packet length	Yes	Table 5-29
0x07	PKTCTRL1	Packet automation control	Yes	Table 5-30
0x08	PKTCTRL0	Packet automation control	Yes	Table 5-31
0x09	ADDR	Device address	Yes	Table 5-32
0x0A	CHANNR	Channel number	Yes	Table 5-33
0x0B	FSCTRL1	Frequency synthesizer control	Yes	Table 5-34
0x0C	FSCTRL0	Frequency synthesizer control	Yes	Table 5-35
0x0D	FREQ2	Frequency control word, high byte	Yes	Table 5-36
0x0E	FREQ1	Frequency control word, middle byte	Yes	Table 5-37
0x0F	FREQ0	Frequency control word, low byte	Yes	Table 5-38
0x10	MDMCFG4	Modem configuration	Yes	Table 5-39
0x11	MDMCFG3	Modem configuration	Yes	Table 5-40
0x12	MDMCFG2	Modem configuration	Yes	Table 5-41
0x13	MDMCFG1	Modem configuration	Yes	Table 5-42
0x14	MDMCFG0	Modem configuration	Yes	Table 5-43
0x15	DEVIATN	Modem deviation setting	Yes	Table 5-44
0x16	MCSM2	Main Radio Control State Machine configuration	Yes	Table 5-45
0x17	MCSM1	Main Radio Control State Machine configuration	Yes	Table 5-46
0x18	MCSM0	Main Radio Control State Machine configuration	Yes	Table 5-47
0x19	FOCCFG	Frequency Offset Compensation configuration	Yes	Table 5-48
0x1A	BSCFG	Bit Synchronization configuration	Yes	Table 5-49
0x1B	AGCCTRL2	AGC control	Yes	Table 5-50
0x1C	AGCCTRL1	AGC control	Yes	Table 5-51
0x1D	AGCCTRL0	AGC control	Yes	Table 5-52
0x1E - 0x1F	Not Used
0x20	RESERVED		Yes	Table 5-53
0x21	FREND1	Front end RX configuration	Yes	Table 5-54
0x22	FREND0	Front end TX configuration	Yes	Table 5-55
0x23	FSCAL3	Frequency synthesizer calibration	Yes	Table 5-56
0x24	FSCAL2	Frequency synthesizer calibration	Yes	Table 5-57
0x25	FSCAL1	Frequency synthesizer calibration	Yes	Table 5-58
0x26	FSCAL0	Frequency synthesizer calibration	Yes	Table 5-59
0x27 - 0x28	Not Used
0x29 - 0x2B	RESERVED		No	Table 5-60
0x2C	TEST2	Various test settings	No	Table 5-63
0x2D	TEST1	Various test settings	No	Table 5-64
0x2E	TEST0	Various test settings	No	Table 5-65

Table 5-21 Status Registers Overview

Address	Register	Description	Details on page number
0x30 (0xF0)	PARTNUM	Part number for CC110L	Table 5-66
0x31 (0xF1)	VERSION	Current version number	Table 5-67
0x32 (0xF2)	FREQEST	Frequency Offset Estimate	Table 5-68
0x33 (0xF3)	CRC_REG	CRC OK	Table 5-69
0x34 (0xF4)	RSSI	Received signal strength indication	Table 5-70
0x35 (0xF5)	MARCSTATE	Control state machine state	Table 5-71
0x36 - 0x37 (0xF6 – 0xF7)	Reserved
0x38 (0xF8)	PKTSTATUS	Current GDOx status and packet status	Table 5-72
0x39 (0xF9)	Reserved
0x3A (0xFA)	TXBYTES	Underflow and number of bytes in the TX FIFO	Table 5-73
0x3B (0xFB)	RXBYTES	Overflow and number of bytes in the RX FIFO	Table 5-74
0x3C - 0x3D (0xFC - 0xFD)	Reserved

Table 5-22 SPI Address Space

	Write		Read
	Single Byte	Burst	Single Byte	Burst
	+0x00	+0x40	+0x80	+0xC0
0x00	IOCFG2				R/W configuration registers, burst access possible
0x01	IOCFG1
0x02	IOCFG0
0x03	FIFOTHR
0x04	SYNC1
0x05	SYNC0
0x06	PKTLEN
0x07	PKTCTRL1
0x08	PKTCTRL0
0x09	ADDR
0x0A	CHANNR
0x0B	FSCTRL1
0x0C	FSCTRL0
0x0D	FREQ2
0x0E	FREQ1
0x0F	FREQ0
0x10	MDMCFG4
0x11	MDMCFG3
0x12	MDMCFG2
0x13	MDMCFG1
0x14	MDMCFG0
0x15	DEVIATN
0x16	MCSM2
0x17	MCSM1
0x18	MCSM0
0x19	FOCCFG
0x1A	BSCFG
0x1B	AGCCTRL2
0x1C	AGCCTRL1
0x1D	AGCCTRL0
0x1E	Not Used
0x1F	Not Used
0x20	RESERVED
0x21	FREND1
0x22	FREND0
0x23	FSCAL3
0x24	FSCAL2
0x25	FSCAL1
0x26	FSCAL0
0x27	Not Used
0x28	Not Used
0x29	RESERVED
0x2A	RESERVED
0x2B	RESERVED
0x2C	TEST2
0x2D	TEST1
0x2E	TEST0
0x2F	Not Used
0x30	SRES		SRES	PARTNUM	Command Strobes, Status registers
0x31	SFSTXON		SFSTXON	VERSION
0x32	SXOFF		SXOFF	FREQEST
0x33	SCAL		SCAL	CRC_REG
0x34	SRX		SRX	RSSI
0x35	STX		STX	MARCSTATE
0x36	SIDLE		SIDLE	Reserved
0x37	Reserved		Reserved	Reserved
0x38	Reserved		Reserved	PKTSTATUS
0x39	SPWD		SPWD	Reserved
0x3A	SFRX		SFRX	TXBYTES
0x3B	SFTX		SFTX	RXBYTES
0x3C	Reserved		Reserved	Reserved
0x3D	SNOP		SNOP	Reserved
0x3E	PATABLE	PATABLE	PATABLE	PATABLE
0x3F	TX FIFO	TX FIFO	RX FIFO	RX FIFO

5.28.1 Configuration Register Details - Registers with preserved values in SLEEP state

Table 5-23 0x00: IOCFG2 - GDO2 Output Pin Configuration

Bit	Field Name	Reset	R/W	Description
7			R0	Not used
6	GDO2_INV	0	R/W	Invert output, that is, select active low (1) / high (0)
5:0	GDO2_CFG[5:0]	41 (101001)	R/W	Default is CHP_RDYn (see Table 5-18).

Table 5-24 0x01: IOCFG1 - GDO1 Output Pin Configuration

Bit	Field Name	Reset	R/W	Description
7	GDO_DS	0	R/W	Set high (1) or low (0) output drive strength on the GDO pins.
6	GDO1_INV	0	R/W	Invert output, that is, select active low (1) / high (0)
5:0	GDO1_CFG[5:0]	46 (101110)	R/W	Default is 3-state (see Table 5-18).

Table 5-25 0x02: IOCFG0 - GDO0 Output Pin Configuration

Bit	Field Name	Reset	R/W	Description
7		0	R/W	Use setting from SmartRF Studio
6	GDO0_INV	0	R/W	Invert output, that is, select active low (1) / high (0)
5:0	GDO0_CFG[5:0]	63 (0x3F)	R/W	Default is CLK_XOSC/192 (see Table 5-18). It is recommended to disable the clock output in initialization, in order to optimize RF performance.

Table 5-26 0x03: FIFOTHR - RX FIFO and TX FIFO Thresholds

Bit	Field Name	Reset	R/W	Description
7		0	R/W	Use setting from SmartRF Studio
6	ADC_RETENTION	0	R/W	0: TEST1 = 0x31 and TEST2= 0x88 when waking up from SLEEP
				1: TEST1 = 0x35 and TEST2 = 0x81 when waking up from SLEEP
				Note that the changes in the TEST registers due to the ADC_RETENTION bit setting are only seen INTERNALLY in the analog part. The values read from the TEST registers when waking up from SLEEP mode will always be the reset value.
				The ADC_RETENTION bit should be set to 1before going into SLEEP mode if settings with an RX filter bandwidth below 325 kHz are wanted at time of wake-up.
5:4	CLOSE_IN_RX[1:0]	0 (00)	R/W	For more details, see DN010 SWRA147
				Setting	RX Attenuation, Typical Values
				0 (00)	0 dB
				1 (01)	6 dB
				2 (10)	12 dB
				3 (11)	18 dB
3:0	FIFO_THR[3:0]	7 (0111)	R/W	Set the threshold for the RX FIFO and TX FIFO. The threshold is exceeded when the number of bytes in the FIFO is equal to or higher than the threshold value.
				Setting	Bytes in RX FIFO	Bytes in TX FIFO
				0 (0000)	4	61
				1 (0001)	8	57
				2 (0010)	12	53
				3 (0011)	16	49
				4 (0100)	20	45
				5 (0101)	24	41
				6 (0110)	28	37
				7 (0111)	32	33
				8 (1000)	36	29
				9 (1001)	40	25
				10 (1010)	44	21
				11 (1011)	48	17
				12 (1100)	52	13
				13 (1101)	56	9
				14 (1110)	60	5
				15 (1111)	64	1

Table 5-27 0x04: SYNC1 - Sync Word, High Byte

Bit	Field Name	Reset	R/W	Description
7:0	SYNC[15:8]	211 (0xD3)	R/W	8 MSB of 16-bit sync word

Table 5-28 0x05: SYNC0 - Sync Word, Low Byte

Bit	Field Name	Reset	R/W	Description
7:0	SYNC[7:0]	145 (0x91)	R/W	8 LSB of 16-bit sync word

Table 5-29 0x06: PKTLEN - Packet Length

Bit	Field Name	Reset	R/W	Description
7:0	PACKET_LENGTH	255 (0xFF)	R/W	Indicates the packet length when fixed packet length mode is enabled. If variable packet length mode is used, this value indicates the maximum packet length allowed. This value must be different from 0.

Table 5-30 0x07: PKTCTRL1 - Packet Automation Control

Bit	Field Name	Reset	R/W	Description
7:5		0 (000)	R/W	Use setting from SmartRF Studio
4		0	R0	Not Used.
3	CRC_AUTOFLUSH	0	R/W	Enable automatic flush of RX FIFO when CRC is not OK. This requires that only one packet is in the RX FIFO and that packet length is limited to the RX FIFO size.
2	APPEND_STATUS	1	R/W	When enabled, two status bytes will be appended to the payload of the packet. The status bytes contain the RSSI value, as well as CRC OK.
1:0	ADR_CHK[1:0]	0 (00)	R/W	Controls address check configuration of received packages.
				Setting	Address check configuration
				0 (00)	No address check
				1 (01)	Address check, no broadcast
				2 (10)	Address check and 0 (0x00) broadcast
				3 (11)	Address check and 0 (0x00) and 255 (0xFF) broadcast

Table 5-31 0x08: PKTCTRL0 - Packet Automation Control

Bit	Field Name	Reset	R/W	Description
7			R0	Not used
6		1	R/W	Use setting from SmartRF Studio
5:4	PKT_FORMAT[1:0]	0 (00)	R/W	Format of RX data
				Setting	Packet format
				0 (00)	Normal mode, use FIFOs for RX and TX
				1 (01)	Synchronous serial mode. Data in on GDO0 and data out on either of the GDOx pins
				2 (10)	Random TX mode; sends random data using PN9 generator. Used for test. Works as normal mode, setting 0 (00), in RX
				3 (11)	Asynchronous serial mode. Data in on GDO0 and data out on either of the GDOx pins
3		0	R0	Not used
2	CRC_EN	1	R/W	1: CRC calculation enabled
2	CRC_EN	1	R/W	0: CRC calculation disabled
1:0	LENGTH_CONFIG[1:0]	1 (01)	R/W	Configure the packet length
				Setting	Packet length configuration
				0 (00)	Fixed packet length mode. Length configured in PKTLEN register
				1 (01)	Variable packet length mode. Packet length configured by the first byte after sync word
				2 (10)	Infinite packet length mode
				3 (11)	Reserved

Table 5-32 0x09: ADDR - Device Address

Bit	Field Name	Reset	R/W	Description
7:0	DEVICE_ADDR[7:0]	0 (0x00)	R/W	Address used for packet filtration. Optional broadcast addresses are 0 (0x00) and 255 (0xFF).

Table 5-33 0x0A: CHANNR - Channel Number

Bit	Field Name	Reset	R/W	Description
7:0	CHAN[7:0]	0 (0x00)	R/W	The 8-bit unsigned channel number, which is multiplied by the channel spacing setting and added to the base frequency.

Table 5-34 0x0B: FSCTRL1 - Frequency Synthesizer Control

Bit	Field Name	Reset	R/W	Description
7:6			R0	Not used
5		0	R/W	Use setting from SmartRF Studio
4:0	FREQ_IF[4:0]	15 (01111)	R/W	The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. The default value gives an IF frequency of 381kHz, assuming a 26.0 MHz crystal.

Table 5-35 0x0C: FSCTRL0 - Frequency Synthesizer Control

Bit	Field Name	Reset	R/W	Description
7:0	FREQOFF[7:0]	0 (0x00)	R/W	Frequency offset added to the base frequency before being used by the frequency synthesizer. (2s-complement). Resolution is FXTAL/2¹⁴ (1.59kHz-1.65kHz); range is ±202 kHz to ±210 kHz, dependent of XTAL frequency.

Table 5-36 0x0D: FREQ2 - Frequency Control Word, High Byte

Bit	Field Name	Reset	R/W	Description
7:6	FREQ[23:22]	0 (00)	R	FREQ[23:22] is always 0 (the FREQ2 register is less than 36 with 26 - 27 MHz crystal)
5:0	FREQ[21:16]	30 (011110)	R/W	FREQ[23:0] is the base frequency for the frequency synthesizer in increments of fXOSC/2¹⁶.

Table 5-37 0x0E: FREQ1 - Frequency Control Word, Middle Byte

Bit	Field Name	Reset	R/W	Description
7:0	FREQ[15:8]	196 (0xC4)	R/W	See Table 5-36.

Table 5-38 0x0F: FREQ0 - Frequency Control Word, Low Byte

Bit	Field Name	Reset	R/W	Description
7:0	FREQ[7:0]	236 (0xEC)	R/W	See Table 5-36.

Table 5-39 0x10: MDMCFG4 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7:6	CHANBW_E[1:0]	2 (10)	R/W
5:4	CHANBW_M[1:0]	0 (00)	R/W	Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. The default values give 203 kHz channel filter bandwidth, assuming a 26.0 MHz crystal.
3:0	DRATE_E[3:0]	12 (1100)	R/W	The exponent of the user specified symbol rate

Table 5-40 0x11: MDMCFG3 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7:0	DRATE_M[7:0]	34 (0x22)	R/W	The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. The 9th bit is a hidden '1'. The resulting data rate is: The default values give a data rate of 115.051 kBaud (closest setting to 115.2 kBaud), assuming a 26.0 MHz crystal.

Table 5-41 0x12: MDMCFG2 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7	DEM_DCFILT_OFF	0	R/W	Disable digital DC blocking filter before demodulator.
				0 = Enable (better sensitivity)
				1 = Disable (current optimized). Only for data rates ≤ 250 kBaud
				The recommended IF frequency changes when the DC blocking is disabled. Use SmartRF Studio to calculate correct register setting.
6:4	MOD_FORMAT[2:0]	0 (000)	R/W	The modulation format of the radio signal
				Setting	Modulation format
				0 (000)	2-FSK
				1 (001)	GFSK
				2 (010)	Reserved
				3 (011)	OOK
				4 (100)	4-FSK
				5 (101)	Reserved
				6 (110)	Reserved
				7 (111)	Reserved
				4-FSK modulation cannot be used together with Manchester encoding
3	MANCHESTER_EN	0	R/W	Enables Manchester encoding/decoding.
				0 = Disable
				1 = Enable
				Manchester encoding cannot be used when using asynchronous serial mode or 4-FSK modulation
2:0	SYNC_MODE[2:0]	2 (010)	R/W	Combined sync-word qualifier mode.
				The values 0 and 4 disables preamble and sync word detection
				The values 1, 2, 5, and 6 enables 16-bit sync word detection. Only 15 of 16 bits need to match when using setting 1 or 5. The values 3 and 7 enables 32-bits sync word detection (only 30 of 32 bits need to match).
				Setting	Sync-word qualifier mode
				0 (000)	No preamble/sync
				1 (001)	15/16 sync word bits detected
				2 (010)	16/16 sync word bits detected
				3 (011)	30/32 sync word bits detected
				4 (100)	No preamble/sync, carrier-sense above threshold
				5 (101)	15/16 + carrier-sense above threshold
				6 (110)	16/16 + carrier-sense above threshold
				7 (111)	30/32 + carrier-sense above threshold

Table 5-42 0x13: MDMCFG1 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7		0	R/W	Use setting from SmartRF Studio
6:4	NUM_PREAMBLE[2:0]	2 (010)	R/W	Sets the minimum number of preamble bytes to be transmitted
				Setting	Number of preamble bytes
				0 (000)	2
				1 (001)	3
				2 (010)	4
				3 (011)	6
				4 (100)	8
				5 (101)	12
				6 (110)	16
				7 (111)	24
3:2			R0	Not used
1:0	CHANSPC_E[1:0]	2 (10)	R/W	2 bit exponent of channel spacing

Table 5-43 0x14: MDMCFG0 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7:0	CHANSPC_M[7:0]	248 (0xF8)	R/W	8-bit mantissa of channel spacing. The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format: The default values give 199.951 kHz channel spacing (the closest setting to 200 kHz), assuming 26.0 MHz crystal frequency.

Table 5-44 0x15: DEVIATN - Modem Deviation Setting

Bit	Field Name	Reset	R/W	Description
7			R0	Not used.
6:4	DEVIATION_E[2:0]	4 (100)	R/W	Deviation exponent.
3			R0	Not used.
2:0	DEVIATION_M[2:0]	7 (111)	R/W	RX
				2-FSK/GFSK/4-FSK	Specifies the expected frequency deviation of incoming signal, must be approximately right for demodulation to be performed reliably and robustly.
				OOK	This setting has no effect.
				TX
				2-FSK/GFSK/4-FSK	Specifies the nominal frequency deviation from the carrier for a '0' (-DEVIATN) and '1' (+DEVIATN) in a mantissa- exponent format, interpreted as a 4-bit value with MSB implicit 1. The resulting frequency deviation is given by: The default values give ±47.607 kHz deviation assuming 26.0 MHz crystal frequency.
				OOK	This setting has no effect

Table 5-45 0x16: MCSM2 - Main Radio Control State Machine Configuration

Bit	Field Name	Reset	R/W	Description
7:5			R0	Not used
4	RX_TIME_RSSI	0	R/W	Direct RX termination based on RSSI measurement (carrier sense). For OOK modulation, RX times out if there is no carrier sense in the first 8 symbol periods.
3:0		7 (0111)	R/W	Use setting from SmartRF Studio

Table 5-46 0x17: MCSM1 - Main Radio Control State Machine Configuration

Bit	Field Name	Reset	R/W	Description
7:6			R0	Not used
5:4	CCA_MODE	3 (11)	R/W	Selects CCA_MODE; Reflected in CCA signal
				Setting	Clear channel indication
				0 (00)	Always
				1 (01)	If RSSI below threshold
				2 (10)	Unless currently receiving a packet
				3 (11)	If RSSI below threshold unless currently receiving a packet
3:2	RXOFF_MODE[1:0]	0 (00)	R/W	Select what should happen when a packet has been received.
				Setting	Next state after finishing packet reception
				0 (00)	IDLE
				1 (01)	FSTXON
				2 (10)	TX
				3 (11)	Stay in RX
1:0	TXOFF_MODE[1:0]	0 (00)	R/W	Select what should happen when a packet has been sent
				Setting	Next state after finishing packet transmission
				0 (00)	IDLE
				1 (01)	FSTXON
				2 (10)	Stay in TX (start sending preamble)
				3 (11)	RX

Table 5-47 0x18: MCSM0 - Main Radio Control State Machine Configuration

Bit	Field Name	Reset	R/W	Description
7:6			R0	Not used
5:4	FS_AUTOCAL[1:0]	0 (00)	R/W	Automatically calibrate when going to RX or TX, or back to IDLE
				Setting	When to perform automatic calibration
				0 (00)	Never (manually calibrate using SCAL strobe)
				1 (01)	When going from IDLE to RX or TX (or FSTXON)
				2 (10)	When going from RX or TX back to IDLE automatically
				3 (11)	Every 4th time when going from RX or TX to IDLE automatically
3:2	PO_TIMEOUT	1 (01)	R/W	Programs the number of times the six-bit ripple counter must expire after the XOSC has settled before CHP_RDYn goes low.⁽¹⁾ If XOSC is on (stable) during power-down, PO_TIMEOUT shall be set so that the regulated digital supply voltage has time to stabilize before CHP_RDYn goes low (PO_TIMEOUT=2 recommended). Typical start-up time for the voltage regulator is 50 μs. For robust operation it is recommended to use PO_TIMEOUT = 2 or 3 when XOSC is off during power-down.
				Setting	Expire count	Timeout after XOSC start
				0 (00)	1	Approximately 2.3 - 2.4 μs
				1 (01)	16	Approximately 37 - 39 μs
				2 (10)	64	Approximately 149 - 155 μs
				3 (11)	256	Approximately 597 - 620 μs
				Exact timeout depends on crystal frequency.
1		0	R/W	Use setting from SmartRF Studio
0	XOSC_FORCE_ON	0	R/W	Force the XOSC to stay on in the SLEEP state.

(1) Note that the XOSC_STABLE signal will be asserted at the same time as the CHIP_RDYn signal; that is, the PO_TIMEOUT delays both signals and does not insert a delay between the signals.

Table 5-48 0x19: FOCCFG - Frequency Offset Compensation Configuration

Bit	Field Name	Reset	R/W	Description
7:6			R0	Not used
5	FOC_BS_CS_GATE	1	R/W	If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CS signal goes high.
4:3	FOC_PRE_K[1:0]	2 (10)	R/W	The frequency compensation loop gain to be used before a sync word is detected.
				Setting	Freq. compensation loop gain before sync word
				0 (00)	K
				1 (01)	2K
				2 (10)	3K
				3 (11)	4K
2	FOC_POST_K	1	R/W	The frequency compensation loop gain to be used after a sync word is detected.
				Setting	Freq. compensation loop gain after sync word
				0	Same as FOC_PRE_K
				1	K/2
1:0	FOC_LIMIT[1:0]	2 (10)	R/W	The saturation point for the frequency offset compensation algorithm:
				Setting	Saturation point (max compensated offset)
				0 (00)	±0 (no frequency offset compensation)
				1 (01)	±BW_CHAN/8
				2 (10)	±BW_CHAN/4
				3 (11)	±BW_CHAN/2
				Frequency offset compensation is not supported for OOK. Always use FOC_LIMIT=0 with this modulation format.

Table 5-49 0x1A: BSCFG - Bit Synchronization Configuration

Bit	Field Name	Reset	R/W	Description
7:6	BS_PRE_KI[1:0]	1 (01)	R/W	The clock recovery feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate):
				Setting	Clock recovery loop integral gain before sync word
				0 (00)	K_I
				1 (01)	2K_I
				2 (10)	3K_I
				3 (11)	4K_I
5:4	BS_PRE_KP[1:0]	2 (10)	R/W	The clock recovery feedback loop proportional gain to be used before a sync word is detected.
				Setting	Clock recovery loop proportional gain before sync word
				0 (00)	K_P
				1 (01)	2K_P
				2 (10)	3K_P
				3 (11)	4K_P
3	BS_POST_KI	1	R/W	The clock recovery feedback loop integral gain to be used after a sync word is detected.
				Setting	Clock recovery loop integral gain after sync word
				0	Same as BS_PRE_KI
				1	K_I /2
2	BS_POST_KP	1	R/W	The clock recovery feedback loop proportional gain to be used after a sync word is detected.
				Setting	Clock recovery loop proportional gain after sync word
				0	Same as BS_PRE_KP
				1	K_P
1:0	BS_LIMIT[1:0]	0 (00)	R/W	The saturation point for the data rate offset compensation algorithm:
				Setting	Data rate offset saturation (max data rate difference)
				0 (00)	±0 (No data rate offset compensation performed)
				1 (01)	±3.125 % data rate offset
				2 (10)	±6.25 % data rate offset
				3 (11)	±12.5 % data rate offset

Table 5-50 0x1B: AGCCTRL2 - AGC Control

Bit	Field Name	Reset	R/W	Description
7:6	MAX_DVGA_GAIN[1:0]	0 (00)	R/W	Reduces the maximum allowable DVGA gain.
				Setting	Allowable DVGA settings
				0 (00)	All gain settings can be used
				1 (01)	The highest gain setting cannot be used
				2 (10)	The 2 highest gain settings cannot be used
				3 (11)	The 3 highest gain settings cannot be used
5:3	MAX_LNA_GAIN[2:0]	0 (000)	R/W	Sets the maximum allowable LNA + LNA 2 gain relative to the maximum possible gain.
				Setting	Maximum allowable LNA + LNA 2 gain
				0 (000)	Maximum possible LNA + LNA 2 gain
				1 (001)	Approximately 2.6 dB below maximum possible gain
				2 (010)	Approximately 6.1 dB below maximum possible gain
				3 (011)	Approximately 7.4 dB below maximum possible gain
				4 (100)	Approximately 9.2 dB below maximum possible gain
				5 (101)	Approximately 11.5 dB below maximum possible gain
				6 (110)	Approximately 14.6 dB below maximum possible gain
				7 (111)	Approximately 17.1 dB below maximum possible gain
2:0	MAGN_TARGET[2:0]	3 (011)	R/W	These bits set the target value for the averaged amplitude from the digital channel filter (1 LSB = 0 dB).
				Setting	Target amplitude from channel filter
				0 (000)	24 dB
				1 (001)	27 dB
				2 (010)	30 dB
				3 (011)	33 dB
				4 (100)	36 dB
				5 (101)	38 dB
				6 (110)	40 dB
				7 (111)	42 dB

Table 5-51 0x1C: AGCCTRL1 - AGC Control

Bit	Field Name	Reset	R/W	Description
7			R0	Not used
6	AGC_LNA_PRIORITY	1	R/W	Selects between two different strategies for LNA and LNA 2 gain adjustment. When 1, the LNA gain is decreased first. When 0, the LNA 2 gain is decreased to minimum before decreasing LNA gain.
5:4	CARRIER_SENSE_REL_THR[1:0]	0 (00)	R/W	Sets the relative change threshold for asserting carrier sense
				Setting	Carrier sense relative threshold
				0 (00)	Relative carrier sense threshold disabled
				1 (01)	6 dB increase in RSSI value
				2 (10)	10 dB increase in RSSI value
				3 (11)	14 dB increase in RSSI value
3:0	CARRIER_SENSE_ABS_THR[3:0]	0 (0000)	R/W	Sets the absolute RSSI threshold for asserting carrier sense. The 2-complement signed threshold is programmed in steps of 1 dB and is relative to the MAGN_TARGET setting.
				Setting	Carrier sense absolute threshold (Equal to channel filter amplitude when AGC has not decreased gain)
				-8 (1000)	Absolute carrier sense threshold disabled
				-7 (1001)	7 dB below MAGN_TARGET setting
				…	…
				-1 (1111)	1 dB below MAGN_TARGET setting
				0 (0000)	At MAGN_TARGET setting
				1 (0001)	1 dB above MAGN_TARGET setting
				…	…
				7 (0111)	7 dB above MAGN_TARGET setting

Table 5-52 0x1D: AGCCTRL0 - AGC Control

Bit	Field Name	Reset	R/W	Description
7:6	HYST_LEVEL[1:0]	2 (10)	R/W	Sets the level of hysteresis on the magnitude deviation (internal AGC signal that determine gain changes).
				Setting	Description
				0 (00)	No hysteresis, small symmetric dead zone, high gain
				1 (01)	Low hysteresis, small asymmetric dead zone, medium gain
				2 (10)	Medium hysteresis, medium asymmetric dead zone, medium gain
				3 (11)	Large hysteresis, large asymmetric dead zone, low gain
5:4	WAIT_TIME[1:0]	1 (01)	R/W	Sets the number of channel filter samples from a gain adjustment has been made until the AGC algorithm starts accumulating new samples.
				Setting	Channel filter samples
				0 (00)	8
				1 (01)	16
				2 (10)	24
				3 (11)	32
3:2	AGC_FREEZE[1:0]	0 (00)	R/W	Control when the AGC gain should be frozen.
				Setting	Function
				0 (00)	Normal operation. Always adjust gain when required.
				1 (01)	The gain setting is frozen when a sync word has been found.
				2 (10)	Manually freeze the analogue gain setting and continue to adjust the digital gain.
				3 (11)	Manually freezes both the analogue and the digital gain setting. Used for manually overriding the gain.
1:0	FILTER_LENGTH[1:0]	1(01)	R/W	2-FSK and 4-FSK: Sets the averaging length for the amplitude from the channel filter. OOK: Sets the OOK decision boundary for OOK reception.
				Setting	Channel filter samples	OOK decision boundary
				0 (00)	8	4 dB
				1 (01)	16	8 dB
				2 (10)	32	12 dB
				3 (11)	64	16 dB

Table 5-53 0x20: RESERVED

Bit	Reset	R/W	Description
7:3	31 (11111)	R/W	Use setting from SmartRF Studio
2		R0	Not used
1:0	0 (00)	R/W	Use setting from SmartRF Studio

Table 5-54 0x21: FREND1 - FrontEnd RX Configuration

Bit	Field Name	Reset	R/W	Description
7:6	LNA_CURRENT[1:0]	1 (01)	R/W	Adjusts front-end LNA PTAT current output
5:4	LNA2MIX_CURRENT[1:0]	1 (01)	R/W	Adjusts front-end PTAT outputs
3:2	LODIV_BUF_CURRENT_RX[1:0]	1 (01)	R/W	Adjusts current in RX LO buffer (LO input to mixer)
1:0	MIX_CURRENT[1:0]	2 (10)	R/W	Adjusts current in mixer

Table 5-55 0x22: FREND0 - FrontEnd TX Configuration

Bit	Field Name	Reset	R/W	Description
7:6			R0	Not used
5:4	LODIV_BUF_CURRENT_TX[1:0]	1 (01)	R/W	Adjusts current TX LO buffer (input to PA). The value to use in this field is given by the SmartRF Studio software .
3			R0	Not used
2:0	PA_POWER[2:0]	0 (000)	R/W	Selects PA power setting. This value is an index to the PATABLE, which can be programmed with up to 2 different PA settings. When using OOK, PA_POWER should be 001, and for all other modulation formats it should be 000, see Section 5.11.

Table 5-56 0x23: FSCAL3 - Frequency Synthesizer Calibration

Bit	Field Name	Reset	R/W	Description
7:6	FSCAL3[7:6]	2 (10)	R/W	Frequency synthesizer calibration configuration. The value to write in this field before calibration is given by the SmartRF Studio software .
5:4	CHP_CURR_CAL_EN[1:0]	2 (10)	R/W	Disable charge pump calibration stage when 0.
3:0	FSCAL3[3:0]	9 (1001)	R/W	Frequency synthesizer calibration result register. Digital bit vector defining the charge pump output current, on an exponential scale: I_OUT = I₀×2^{FSCAL3[3:0]/4} See Section 5.27.2 for more details.

Table 5-57 0x24: FSCAL2 - Frequency Synthesizer Calibration

Bit	Field Name	Reset	R/W	Description
7:6			R0	Not used
5	VCO_CORE_H_EN	0	R/W	Choose high (1) / low (0) VCO
4:0	FSCAL2[4:0]	10 (01010)	R/W	Frequency synthesizer calibration result register. VCO current calibration result and override value. See Section 5.27.2 for more details.

Table 5-58 0x25: FSCAL1 - Frequency Synthesizer Calibration

Bit	Field Name	Reset	R/W	Description
7:6			R0	Not used
5:0	FSCAL1[5:0]	32 (0x20)	R/W	Frequency synthesizer calibration result register. Capacitor array setting for VCO coarse tuning. See Section 5.27.2 for more details.

Table 5-59 0x26: FSCAL0 - Frequency Synthesizer Calibration

Bit	Field Name	Reset	R/W	Description
7			R0	Not used
6:0	FSCAL0[6:0]	13 (0x0D)	R/W	Frequency synthesizer calibration control. The value to use in this register is given by the SmartRF Studio software

5.28.2 Configuration Register Details - Registers that Loose Programming in SLEEP State

Table 5-60 0x29: RESERVED

Bit	Field Name	Reset	R/W	Description
7:0		89 (0x59)	R/W	Use setting from SmartRF Studio

Table 5-61 0x2A: RESERVED

Bit	Field Name	Reset	R/W	Description
7:0		127 (0x7F)	R/W	Use setting from SmartRF Studio

Table 5-62 0x2B: RESERVED

Bit	Field Name	Reset	R/W	Description
7:0		63 (0x3F)	R/W	Use setting from SmartRF Studio

Table 5-63 0x2C: TEST2 - Various Test Settings

Bit	Field Name	Reset	R/W	Description
7:0	TEST2[7:0]	136 (0x88)	R/W	Use setting from SmartRF Studio This register will be forced to 0x88 or 0x81 when it wakes up from SLEEP mode, depending on the configuration of FIFOTHR.ADC_RETENTION. The value read from this register when waking up from SLEEP always is the reset value (0x88) regardless of the ADC_RETENTION setting. The inverting of some of the bits due to the ADC_RETENTION setting is only seen INTERNALLY in the analog part.

Table 5-64 0x2D: TEST1 - Various Test Settings

Bit	Field Name	Reset	R/W	Description
7:0	TEST1[7:0]	49 (0x31)	R/W	Use setting from SmartRF Studio SWRC176 This register will be forced to 0x31 or 0x35 when it wakes up from SLEEP mode, depending on the configuration of FIFOTHR.ADC_RETENTION. The value read from this register when waking up from SLEEP always is the reset value (0x31) regardless of the ADC_RETENTION setting. The inverting of some of the bits due to the ADC_RETENTION setting is only seen INTERNALLY in the analog part.

Table 5-65 0x2E: TEST0 - Various Test Settings

Bit	Field Name	Reset	R/W	Description
7:2	TEST0[7:2]	2 (000010)	R/W	Use setting from SmartRF Studio SWRC176
1	VCO_SEL_CAL_EN	1	R/W	Enable VCO selection calibration stage when 1
0	TEST0[0]	1	R/W	Use setting from SmartRF Studio SWRC176

5.28.3 Status Register Details

Table 5-66 0x30 (0xF0): PARTNUM - Chip ID

Bit	Field Name	Reset	R/W	Description
7:0	PARTNUM[7:0]	0 (0x00)	R	Chip part number

Table 5-67 0x31 (0xF1): VERSION - Chip ID

Bit	Field Name	Reset	R/W	Description
7:0	VERSION[7:0]	23 (0x17)	R	Chip version number. Subject to change without notice.

Table 5-68 0x32 (0xF2): FREQEST - Frequency Offset Estimate from Demodulator

Bit	Field Name	Reset	R/W	Description
7:0	FREQOFF_EST		R	The estimated frequency offset (2s complement) of the carrier. Resolution is F_XTAL/2¹⁴ (1.59 - 1.65 kHz); range is ±202 kHz to ±210 kHz, depending on XTAL frequency. Frequency offset compensation is only supported for 2-FSK, GFSK, and 4- FSK modulation. This register will read 0 when using OOK modulation.

Table 5-69 0x33 (0xF3): CRC_REG - CRC OK

Bit	Field Name	Reset	R/W	Description
7	CRC OK		R	The last CRC comparison matched. Cleared when entering/restarting RX mode.
6:0			R	Reserved

Table 5-70 0x34 (0xF4): RSSI - Received Signal Strength Indication

Bit	Field Name	Reset	R/W	Description
7:0	RSSI		R	Received signal strength indicator

Table 5-71 0x35 (0xF5): MARCSTATE - Main Radio Control State Machine State

Bit	Field Name	R/W	Description
7:5		R0	Not used
4:0	MARC_STATE[4:0]	R	Main Radio Control FSM State
			Value	State name	State (see Figure 5-11)
			0 (0x00)	SLEEP	SLEEP
			1 (0x01)	IDLE	IDLE
			2 (0x02)	XOFF	XOFF
			3 (0x03)	VCOON_MC	MANCAL
			4 (0x04)	REGON_MC	MANCAL
			5 (0x05)	MANCAL	MANCAL
			6 (0x06)	VCOON	FS_WAKEUP
			7 (0x07)	REGON	FS_WAKEUP
			8 (0x08)	STARTCAL	CALIBRATE
			9 (0x09)	BWBOOST	SETTLING
			10 (0x0A)	FS_LOCK	SETTLING
			11 (0x0B)	IFADCON	SETTLING
			12 (0x0C)	ENDCAL	CALIBRATE
			13 (0x0D)	RX	RX
			14 (0x0E)	RX_END	RX
			15 (0x0F)	RX_RST	RX
			16 (0x10)	TXRX_SWITCH	TXRX_SETTLING
			17 (0x11)	RXFIFO_OVERFLOW	RXFIFO_OVERFLOW
			18 (0x12)	FSTXON	FSTXON
			19 (0x13)	TX	TX
			20 (0x14)	TX_END	TX
			21 (0x15)	RXTX_SWITCH	RXTX_SETTLING
			22 (0x16)	TXFIFO_UNDERFLOW	TXFIFO_UNDERFLOW
			Note: it is not possible to read back the SLEEP or XOFF state numbers because setting CSn low will make the chip enter the IDLE mode from the SLEEP or XOFF states.

Table 5-72 0x38 (0xF8): PKTSTATUS - Current GDOx Status and Packet Status

Bit	Field Name	R/W	Description
7	CRC_OK	R	The last CRC comparison matched. Cleared when entering/restarting RX mode.
6	CS	R	Carrier sense. Cleared when entering IDLE mode.
5			Reserved
4	CCA	R	Channel is clear
3	SFD	R	Start of Frame Delimiter. This bit is asserted when sync word has been received and deasserted at the end of the packet. It will also de-assert when a packet is discarded due to address or maximum length filtering or the radio enters RXFIFO_OVERFLOW state.
2	GDO2	R	Current GDO2 value. Note: the reading gives the non-inverted value irrespective of what IOCFG2.GDO2_INV is programmed to. It is not recommended to check for PLL lock by reading PKTSTATUS[2] with GDO2_CFG=0x0A.
1		R	Not used
0	GDO0	R	Current GDO0 value. Note: the reading gives the non-inverted value irrespective of what IOCFG0.GDO0_INV is programmed to. It is not recommended to check for PLL lock by reading PKTSTATUS[0] with GDO0_CFG=0x0A.

Table 5-73 0x3A (0xFA): TXBYTES - Underflow and Number of Bytes

Bit	Field Name	Reset	R/W	Description
7	TXFIFO_UNDERFLOW		R
6:0	NUM_TXBYTES		R	Number of bytes in TX FIFO

Table 5-74 0x3B (0xFB): RXBYTES - Overflow and Number of Bytes

Bit	Field Name	Reset	R/W	Description
7	RXFIFO_OVERFLOW		R
6:0	NUM_RXBYTES		R	Number of bytes in RX FIFO

5.29 Development Kit Ordering Information

Orderable Evaluation Module	Description	Minimum Order Quantity
CC11xLDK-868-915	CC11xL Development Kit, 868/915 MHz	1
CC11xLEMK-433	CC11xL Evaluation Module Kit, 433 MHz	1
RF BoosterPack for MSP430 LaunchPad	Plug-in boards for the MSP430 Value Line LaunchPad (MSP-EXP430G2), 868/915 MHz	1