JAJSG43B June   2012  – September 2018 CC430F5123 , CC430F5125 , CC430F5143 , CC430F5145 , CC430F5147 , CC430F6147

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 CC430F614x Terminal Functions
      2. Table 4-2 CC430F514x and CC430F512x Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Currents
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics – Low-Power Mode Supply Currents
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Thermal Resistance Characteristics, CC430F51xx
    10. 5.10 Thermal Resistance Characteristics, CC430F61xx
    11. 5.11 Digital Inputs
    12. 5.12 Digital Outputs
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    17. 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
    18. 5.18 DCO Frequency
    19. 5.19 PMM, Brownout Reset (BOR)
    20. 5.20 PMM, Core Voltage
    21. 5.21 PMM, SVS High Side
    22. 5.22 PMM, SVM High Side
    23. 5.23 PMM, SVS Low Side
    24. 5.24 PMM, SVM Low Side
    25. 5.25 Wake-up Times From Low-Power Modes and Reset
    26. 5.26 Timer_A
    27. 5.27 USCI (UART Mode) Clock Frequency
    28. 5.28 USCI (UART Mode)
    29. 5.29 USCI (SPI Master Mode) Clock Frequency
    30. 5.30 USCI (SPI Master Mode)
    31. 5.31 USCI (SPI Slave Mode)
    32. 5.32 USCI (I2C Mode)
    33. 5.33 LCD_B Operating Conditions
    34. 5.34 LCD_B Electrical Characteristics
    35. 5.35 10-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 10-Bit ADC, Timing Parameters
    37. 5.37 10-Bit ADC, Linearity Parameters
    38. 5.38 REF, External Reference
    39. 5.39 REF, Built-In Reference
    40. 5.40 Comparator_B
    41. 5.41 Flash Memory
    42. 5.42 JTAG and Spy-Bi-Wire Interface
    43. 5.43 RF1A CC1101-Based Radio Parameters
      1. 5.43.1  RF1A Recommended Operating Conditions
      2. 5.43.2  RF Crystal Oscillator, XT2
      3. 5.43.3  Current Consumption, Reduced-Power Modes
      4. 5.43.4  Current Consumption, Receive Mode
      5. 5.43.5  Current Consumption, Transmit Mode
      6. 5.43.6  Typical TX Current Consumption, 315 MHz, 25°C
      7. 5.43.7  Typical TX Current Consumption, 433 MHz, 25°C
      8. 5.43.8  Typical TX Current Consumption, 868 MHz
      9. 5.43.9  Typical TX Current Consumption, 915 MHz
      10. 5.43.10 RF Receive, Overall
      11. 5.43.11 RF Receive, 315 MHz
      12. 5.43.12 RF Receive, 433 MHz
      13. 5.43.13 RF Receive, 868 MHz and 915 MHz
      14. 5.43.14 Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting
      15. 5.43.15 Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting
      16. 5.43.16 Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting
      17. 5.43.17 Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting
      18. 5.43.18 RF Transmit
      19. 5.43.19 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
      20. 5.43.20 Typical Output Power, 315 MHz
      21. 5.43.21 Typical Output Power, 433 MHz
      22. 5.43.22 Typical Output Power, 868 MHz
      23. 5.43.23 Typical Output Power, 915 MHz
      24. 5.43.24 Frequency Synthesizer Characteristics
      25. 5.43.25 Typical RSSI_offset Values
  6. 6Detailed Description
    1. 6.1  Sub-1 GHz Radio
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Backup RAM
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock
      2. 6.11.2  Power-Management Module (PMM)
      3. 6.11.3  Digital I/O
      4. 6.11.4  Port Mapping Controller
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  DMA Controller
      7. 6.11.7  Watchdog Timer (WDT_A)
      8. 6.11.8  CRC16
      9. 6.11.9  Hardware Multiplier
      10. 6.11.10 AES128 Accelerator
      11. 6.11.11 Universal Serial Communication Interface (USCI)
      12. 6.11.12 TA0
      13. 6.11.13 TA1
      14. 6.11.14 Real-Time Clock (RTC_D)
      15. 6.11.15 Voltage Reference (REF) (Including Output)
      16. 6.11.16 LCD_B (Only CC430F614x)
      17. 6.11.17 Comparator_B
      18. 6.11.18 ADC10_A (CC430F614x and CC430F514x Only)
      19. 6.11.19 Embedded Emulation Module (EEM) (S Version)
      20. 6.11.20 Peripheral File Map
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 to P1.4) Input/Output With Schmitt Trigger
      2. 6.12.2  Port P1 (P1.5 to P1.7) Input/Output With Schmitt Trigger
      3. 6.12.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.12.4  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (CC430F614x Only)
      6. 6.12.6  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      7. 6.12.7  Port P5 (P5.2 to P5.4) Input/Output With Schmitt Trigger (CC430F614x Only)
      8. 6.12.8  Port P5 (P5.5 to P5.7) Input/Output With Schmitt Trigger (CC430F614x Only)
      9. 6.12.9  Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      10. 6.12.10 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptor Structure
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Circuits
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  Device Nomenclature
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VEREF+ Positive built-in reference voltage REFVSEL = \{2\} for 2.5 V,
REFON = REFOUT = 1
3 V 2.5 ±1.5% V
REFVSEL = \{1\} for 2 V,
REFON = REFOUT = 1
3 V 2.01 ±1.5%
REFVSEL = \{0\} for 1.5 V,
REFON = REFOUT = 1
2.2 V, 3 V 1.505 ±1.5%
AVCC(min) AVCC minimum voltage, Positive built-in reference active REFVSEL = \{0\} for 1.5 V 1.8 V
REFVSEL = \{1\} for 2 V 2.3
REFVSEL = \{2\} for 2.5 V 2.8
IREF+ Operating supply current into AVCC terminal(1) fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = \{0\} for 1.5 V
3 V 15.5 19 µA
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = \{1\} for 2 V
3 V 18 24
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = \{2\} for 2.5 V
3 V 21 30
IREF+,REFOUT Operating supply current into AVCC terminal with REF output buffer enabled REFON = 1, REFOUT = 1,
REFBURST = 0
3 V 0.9 1.7 mA
IL(VREF+) Load-current regulation, VREF+ terminal(2) REFVSEL = \{0, 1, 2\},
ILoad,VREF+ = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level, REFON = REFOUT = 1
2500 µV/mA
CVREF+ Capacitance at VREF+ terminals REFON = REFOUT = 1 20 100 pF
TCREF+ Temperature coefficient of built-in reference(3) REFVSEL = \{0, 1, 2\}, REFON = 1 30 50 ppm/ °C
ISENSOR Operating supply current into AVCC terminal(5) REFON = 0, INCH = 0Ah,
ADC10ON = NA, TA = 30°C
2.2 V 150 180 µA
3 V 150 190
VSENSOR See (6) ADC10ON = 1, INCH = 0Ah, TA = 30°C 2.2 V 765 mV
3 V 765
VMID AVCC divider at channel 11 ADC10ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
2.2 V 1.06 1.1 1.14 V
3 V 1.46 1.5 1.54
tSENSOR (sample) Sample time required if channel 10 is selected(7) ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
30 µs
tVMID (sample) Sample time required if channel 11 is selected(8) ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
1 µs
PSRR_DC Power supply rejection ratio (DC) AVCC = AVCC(min) to AVCC(max),
TA = 25°C,
REFVSEL = \{0, 1, 2\}, REFON = 1
120 300 µV/V
PSRR_AC Power supply rejection ratio (AC) AVCC = AVCC(min) to AVCC(max),
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = (0, 1, 2\}, REFON = 1
6.4 mV/V
tSETTLE Settling time of reference voltage(4) AVCC = AVCC(min) to AVCC(max),
REFVSEL = \{0, 1, 2\}, REFON = 0 → 1
TA = –40°C to 85°C 23 125 µs
TA = 25°C 23 50
TA = 85°C 16 25
The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an analog-to-digital conversion.
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace and other factors. Positive load currents are flowing into the device.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
CC430F6147 CC430F6145 CC430F6143 CC430F5147 CC430F5145 CC430F5143 CC430F5125 CC430F5123 vtemp_vs_temp.gifFigure 5-21 Typical Temperature Sensor Voltage