JAJSGU2B January   2019  – May 2022 DLP4500

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Chipset Component Usage Specification
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
    5. 8.5 Micromirror Array Temperature Calculation
      1. 8.5.1 Package Thermal Resistance
      2. 8.5.2 Case Temperature
        1. 8.5.2.1 Temperature Calculation
    6. 8.6 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.6.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.6.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLPC350 System Interfaces
          1. 9.2.2.1.1 Control Interface
          2. 9.2.2.1.2 Input Data Interface
        2. 9.2.2.2 DLPC350 System Output Interfaces
          1. 9.2.2.2.1 Illumination Interface
          2. 9.2.2.2.2 Trigger Interface (Sync Outputs)
        3. 9.2.2.3 DLPC350 System Support Interfaces
          1. 9.2.2.3.1 Reference Clock
          2. 9.2.2.3.2 PLL
          3. 9.2.2.3.3 Program Memory Flash Interface
        4. 9.2.2.4 DMD Interfaces
          1. 9.2.2.4.1 DLPC350 to DMD Digital Data
          2. 9.2.2.4.2 DLPC350 to DMD Control Interface
          3. 9.2.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing Requirements
    2. 10.2 DMD Power Supply Power-Up Procedure
    3. 10.3 DMD Power Supply Power-Down Procedure
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DMD Interface Design Considerations
      2. 11.1.2 DMD Termination Requirements
      3. 11.1.3 Decoupling Capacitors
      4. 11.1.4 Power Plane Recommendations
      5. 11.1.5 Signal Layer Recommendations
      6. 11.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 11.1.7 PCB Manufacturing
        1. 11.1.7.1 General Guidelines
        2. 11.1.7.2 Trace Widths and Minimum Spacings
        3. 11.1.7.3 Routing Constraints
        4. 11.1.7.4 Fiducials
        5. 11.1.7.5 Flex Considerations
        6. 11.1.7.6 DLPC350 Thermal Considerations
    2. 11.2 Layout Example
      1. 11.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 11.2.3 Recommended DLPC350 PLL Layout Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Device Nomenclature
    2. 12.2 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 サポート・リソース
    6.     Trademarks
    7. 12.6 Electrostatic Discharge Caution
    8. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Electrical Characteristics

over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
IIL Low-level input current (1) VREF = 2.00 V, VI = 0 V –50 nA
IIH High-level input current (1) VREF = 2.00 V, VI = VREF 50 nA
CURRENT
IREF Current into VREF pin VREF = 2.00 V, fDCLK = 120 MHz 2.15 2.75 mA
ICC Current into VCC pin VCC = 2.75 V, fDCLK = 120 MHz 125 160 mA
IOFFSET Current into VOFFSET pin (2) VOFFSET = 8.75 V, Three global resets within time period = 200 μs 3 3.3 mA
IBIAS Current into VBIAS pin (2) (3) VBIAS = 16.5 V, Three global resets within time period = 200 μs 2.55 6.5 mA
IRESET Current into VRESET pin VRESET = –10.5 V 2.45 3.1 mA
ITOTAL 135.15 175.65 mA
POWER
PREF Power into VREF pin (4) VREF = 2.00 V, fDCLK = 120 MHz 4.15 5.5 mW
PCC Power into VCC pin (4) VCC = 2.75 V, fDCLK = 120 MHz 343.75 440 mW
POFFSET Power into VOFFSET pin (4) VOFFSET = 8.75 V, Three global resets within time period = 200 μs 26.25 28.9 mW
PBIAS Power into VBIAS pin (4) VBIAS = 16.5 V, Three global resets within time period = 200 μs 42.1 58.6 mW
PRESET Power into VRESET pin (4) VRESET = –10.5 V 25.71 32.6 mW
PTOTAL 442 566 mW
CAPACITANCE
CI Input capacitance ƒ = 1 MHz 10 pF
CO Output capacitance ƒ = 1 MHz 10 pF
(1) Applies to LVCMOS pins only. LVCMOS pins do not have pullup or pulldown configurations.
(2) Exceeding the maximum allowable absolute voltage difference between VBIAS and VOFFSET may result in excess current draw. See the Section 7.1 for further details.
(3) When DRC_OE = HIGH, the internal reset drivers are tri-stated and IBIAS standby current is 6.5 mA.
(4) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See the Section 8.5 for further details.