JAJSGU2B January   2019  – May 2022 DLP4500

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Chipset Component Usage Specification
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
    5. 8.5 Micromirror Array Temperature Calculation
      1. 8.5.1 Package Thermal Resistance
      2. 8.5.2 Case Temperature
        1. 8.5.2.1 Temperature Calculation
    6. 8.6 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.6.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.6.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLPC350 System Interfaces
          1. 9.2.2.1.1 Control Interface
          2. 9.2.2.1.2 Input Data Interface
        2. 9.2.2.2 DLPC350 System Output Interfaces
          1. 9.2.2.2.1 Illumination Interface
          2. 9.2.2.2.2 Trigger Interface (Sync Outputs)
        3. 9.2.2.3 DLPC350 System Support Interfaces
          1. 9.2.2.3.1 Reference Clock
          2. 9.2.2.3.2 PLL
          3. 9.2.2.3.3 Program Memory Flash Interface
        4. 9.2.2.4 DMD Interfaces
          1. 9.2.2.4.1 DLPC350 to DMD Digital Data
          2. 9.2.2.4.2 DLPC350 to DMD Control Interface
          3. 9.2.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing Requirements
    2. 10.2 DMD Power Supply Power-Up Procedure
    3. 10.3 DMD Power Supply Power-Down Procedure
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DMD Interface Design Considerations
      2. 11.1.2 DMD Termination Requirements
      3. 11.1.3 Decoupling Capacitors
      4. 11.1.4 Power Plane Recommendations
      5. 11.1.5 Signal Layer Recommendations
      6. 11.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 11.1.7 PCB Manufacturing
        1. 11.1.7.1 General Guidelines
        2. 11.1.7.2 Trace Widths and Minimum Spacings
        3. 11.1.7.3 Routing Constraints
        4. 11.1.7.4 Fiducials
        5. 11.1.7.5 Flex Considerations
        6. 11.1.7.6 DLPC350 Thermal Considerations
    2. 11.2 Layout Example
      1. 11.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 11.2.3 Recommended DLPC350 PLL Layout Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Device Nomenclature
    2. 12.2 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 サポート・リソース
    6.     Trademarks
    7. 12.6 Electrostatic Discharge Caution
    8. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-F3ABCEB6-B05F-44E7-B6EE-8AEC60CBD391-low.png Figure 6-1 FQE Package. LCCC (80). Bottom View.

Connector Pins for FQE

PIN TYPE SIGNAL DATA RATE (1) INTERNAL TERMINATION DESCRIPTION TRACE (mm) (2)
NAME NO.
DATA INPUTS
DATA(0) C12 Input LVCMOS DDR none Input data bus, bit 0, LSB 8.11
DATA(1) C10 Input LVCMOS DDR none Input data bus, bit 1 7.82
DATA(2) C9 Input LVCMOS DDR none Input data bus, bit 2 7.88
DATA(3) C7 Input LVCMOS DDR none Input data bus, bit 3 7.84
DATA(4) C4 Input LVCMOS DDR none Input data bus, bit 4 8.10
DATA(5) C6 Input LVCMOS DDR none Input data bus, bit 5 7.89
DATA(6) C3 Input LVCMOS DDR none Input data bus, bit 6 7.87
DATA(7) C13 Input LVCMOS DDR none Input data bus, bit 7 7.84
DATA(8) C15 Input LVCMOS DDR none Input data bus, bit 8 8.13
DATA(9) C16 Input LVCMOS DDR none Input data bus, bit 9 8.00
DATA(10) C18 Input LVCMOS DDR none Input data bus, bit 10 8.12
DATA(11) C19 Input LVCMOS DDR none Input data bus, bit 11 8.08
DATA(12) C21 Input LVCMOS DDR none Input data bus, bit 12 9.27
DATA(13) C22 Input LVCMOS DDR none Input data bus, bit 13 9.47
DATA(14) D22 Input LVCMOS DDR none Input data bus, bit 14 9.46
DATA(15) D21 Input LVCMOS DDR none Input data bus, bit 15 8.73
DATA(16) D19 Input LVCMOS DDR none Input data bus, bit 16 8.10
DATA(17) D4 Input LVCMOS DDR none Input data bus, bit 17 8.02
DATA(18) D9 Input LVCMOS DDR none Input data bus, bit 18 8.07
DATA(19) D10 Input LVCMOS DDR none Input data bus, bit 19 7.91
DATA(20) D6 Input LVCMOS DDR none Input data bus, bit 20 8.52
DATA(21) D16 Input LVCMOS DDR none Input data bus, bit 21 9.10
DATA(22) D7 Input LVCMOS DDR none Input data bus, bit 22 8.00
DATA(23) D15 Input LVCMOS DDR none Input data bus, bit 23, MSB 8.61
DCLK D13 Input LVCMOS DDR none Input data bus clock 8.63
DATA CONTROL INPUTS
LOADB D12 Input LVCMOS DDR none Parallel-data load enable 8.65
TRC D3 Input LVCMOS DDR none Input-data toggle-rate control 4.67
SCTRL D18 Input LVCMOS DDR none Serial control bus 9.40
SAC_BUS D33 Input LVCMOS — none Stepped address-control serial-bus data 6.56
SAC_CLK D29 Input LVCMOS — none Stepped address-control serial bus clock 8.07
MIRROR RESET CONTROL INPUTS
DRC_BUS C29 Input LVCMOS — none DMD reset-control serial bus 8.24
DRC_OE C33 Input LVCMOS — none Active-low output enable signal for internal DMD reset driver circuitry 4.43
DRC_STROBE C36 Input LVCMOS — none Strobe signal for DMD reset control inputs 9.20
POWER INPUTS (3)
VBIAS C31 Power none Mirror-reset bias voltage
VBIAS C32 Power
VOFFSET D25 Power none Mirror-reset offset voltage
VOFFSET D26 Power
VRESET D31 Power none Mirror-reset voltage
VRESET D32 Power
VREF C25 Power none Power supply for low-voltage CMOS double-data-rate (DDR) interface
VREF C26 Power
VCC C1 Power none Power supply for LVCMOS logic
VCC C2 Power
VCC C34 Power
VCC C35 Power
VCC C37 Power
VCC C38 Power
VCC C39 Power
VCC C40 Power
VCC D1 Power
VCC D2 Power
VCC D34 Power
VCC D35 Power
VCC D37 Power
VCC D38 Power
VCC D39 Power
VCC D40 Power
VSS C5 Power none Ground – Common return for all power inputs
VSS C8 Power
VSS C11 Power
VSS C14 Power
VSS C17 Power
VSS C20 Power
VSS C23 Power
VSS C24 Power
VSS C27 Power
VSS C28 Power
VSS C30 Power
VSS D5 Power
VSS D8 Power
VSS D11 Power
VSS D14 Power
VSS D17 Power
VSS D20 Power
VSS D23 Power
VSS D24 Power
VSS D27 Power
VSS D28 Power
VSS D30 Power
(1)
  • DDR = Double data rate
  • SDR = Single data rate
  • Refer to Timing Requirements for specifications and relationships.
(2) Net trace lengths inside the package:
  • Relative dielectric constant for the FQE package is 9.8.
  • Propagation speed = 11.8 / √(9.8) = 3.769 inches/ns.
  • Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VSS, VCC, VOFFSET, VBIAS, VRESET.
Table 6-1 Connector Pins for FQE
NAME PIN SIGNAL DESCRIPTION
UNUSED A1 thru A25 Test pads Do not connect
B1 thru B25
D36
E1 thru E25
F1 thru F25
GUID-410B5159-C8AA-437C-AE22-DE28F3769334-low.png Figure 6-2 FQD Package LCCC (98) Bottom View
Table 6-2 Connector Pins for FQD
PIN TYPE SIGNAL DATA RATE (1) INTERNAL TERMINATION DESCRIPTION PACKAGE NET LENGTH (mm) (2)
NAME NO.
DATA INPUTS
DATA(0) A1 Input LVCMOS DDR none Input data bus, bit 0, LSB 3.77
DATA(1) A2 Input LVCMOS DDR none Input data bus, bit 1 3.77
DATA(2) A3 Input LVCMOS DDR none Input data bus, bit 2 3.73
DATA(3) A4 Input LVCMOS DDR none Input data bus, bit 3 3.74
DATA(4) B1 Input LVCMOS DDR none Input data bus, bit 4 3.79
DATA(5) B3 Input LVCMOS DDR none Input data bus, bit 5 3.75
DATA(6) C1 Input LVCMOS DDR none Input data bus, bit 6 3.72
DATA(7) C3 Input LVCMOS DDR none Input data bus, bit 7 3.75
DATA(8) C4 Input LVCMOS DDR none Input data bus, bit 8 3.78
DATA(9) D1 Input LVCMOS DDR none Input data bus, bit 9 3.75
DATA(10) D4 Input LVCMOS DDR none Input data bus, bit 10 3.77
DATA(11) E1 Input LVCMOS DDR none Input data bus, bit 11 3.75
DATA(12) E4 Input LVCMOS DDR none Input data bus, bit 12 3.71
DATA(13) F1 Input LVCMOS DDR none Input data bus, bit 13 3.76
DATA(14) F3 Input LVCMOS DDR none Input data bus, bit 14 3.73
DATA(15) G1 Input LVCMOS DDR none Input data bus, bit 15 3.72
DATA(16) G2 Input LVCMOS DDR none Input data bus, bit 16 3.77
DATA(17) G4 Input LVCMOS DDR none Input data bus, bit 17 3.73
DATA(18) H1 Input LVCMOS DDR none Input data bus, bit 18 3.74
DATA(19) H2 Input LVCMOS DDR none Input data bus, bit 19 3.76
DATA(20) H4 Input LVCMOS DDR none Input data bus, bit 20 3.70
DATA(21) J1 Input LVCMOS DDR none Input data bus, bit 21 3.77
DATA(22) J3 Input LVCMOS DDR none Input data bus, bit 22 3.76
DATA(23) J4 Input LVCMOS DDR none Input data bus, bit 23, MSB 3.77
DCLK K1 Input LVCMOS DDR none Input data bus clock 3.74
DATA CONTROL INPUTS
LOADB K2 Input LVCMOS DDR none Parallel-data load enable 3.74
TRC K4 Input LVCMOS DDR none Input-data toggle rate control 4.70
SCTRL K3 Input LVCMOS DDR none Serial-control bus 3.75
SAC_BUS C20 Input LVCMOS — none Stepped address-control serial-bus data 3.77
SAC_CLK C22 Input LVCMOS — none Stepped address-control serial-bus clock 1.49
MIRROR RESET CONTROL INPUTS
DRC_BUS B21 Input LVCMOS — none DMD reset-control serial bus 3.73
DRC_OE A20 Input LVCMOS — none Active-low output enable signal for internal DMD reset driver circuitry 3.74
DRC_STROBE A22 Input LVCMOS — none Strobe signal for DMD reset-control inputs 3.73
POWER INPUTS (3)
VBIAS C19 Power Mirror-reset bias voltage
VBIAS D19 Power
VOFFSET A19 Power Mirror-reset offset voltage
VOFFSET K19 Power
VRESET E19 Power Mirror-reset voltage
VRESET F19 Power
VREF B19 Power Power supply for LVCMOS double-data-rate (DDR) interface
VREF J19 Power
VCC B22 Power Power supply for LVCMOS logic
VCC C2 Power
VCC D21 Power
VCC E2 Power
VCC E20 Power
VCC E22 Power
VCC F21 Power
VCC G3 Power
VCC G19 Power
VCC G20 Power
VCC G22 Power
VCC H19 Power
VCC H21 Power
VCC J20 Power
VCC J22 Power
VCC K21 Power
VSS A21 Power Ground – Common return for all power inputs
VSS B2 Power
VSS B4 Power
VSS B20 Power
VSS C21 Power
VSS D2 Power
VSS D3 Power
VSS D20 Power
VSS D22 Power
VSS E3 Power
VSS E21 Power
VSS F2 Power
VSS F4 Power
VSS F20 Power
VSS F22 Power
VSS G21 Power
VSS H3 Power
VSS H20 Power
VSS H22 Power
VSS J2 Power
VSS J21 Power
VSS K20 Power
(1)
  • DDR = Double data rate
  • SDR = Single data rate
  • Refer to Timing Requirements for specifications and relationships.
(2) Net trace lengths inside the package:
  • Relative dielectric constant for the FQD ceramic package is 9.8.
  • Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns.
  • Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VSS, VCC, VOFFSET, VBIAS, VRESET.
Table 6-3 Pin Configuration and Functions – Test Pads for FQD Package
NAME PIN SIGNAL DESCRIPTION
UNUSED A5, A18, B5, B18, C5, C18, D5, D18, E5, E18, F5, F18, G5, G18, H5, H18, J5, J18, K22 Test pads Do not connect