JAJSGT9G April   2010  – January 2019 DLP5500

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Window Characteristics
    12. 7.12 Chipset Component Usage Specification
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Video Modes
      2. 8.4.2 Structured Light Modes
        1. 8.4.2.1 Static Image Buffer Mode
        2. 8.4.2.2 Real Time Structured Light Mode
    5. 8.5 Window Characteristics and Optics
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation for Uniform Illumination
    7. 8.7 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLP5500 System Interface
  10. 10Power Supply Recommendations
    1. 10.1 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連資料
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • FYA|149
サーマルパッド・メカニカル・データ
発注情報

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage(1), See Figure 2 VCC = 3.0 V, IOH = –20 mA 2.4 V
VOL Low-level output voltage(1), See Figure 2 VCC = 3.6 V, IOL = 15 mA 0.4 V
IOZ High impedance output current(1) VCC = 3.6 V 10 µA
IIL Low-level input current(1) VCC = 3.6 V, VI = 0 V –60 µA
IIH High-level input current(1) VCC = 3.6 V, VI = VCC 200 µA
ICC Current into VCC pin VCC = 3.6 V, 750 mA
ICCI Current into VOFFSET pin(2) VCCI = 3.6 V 450 mA
ICC2 Current into VCC2 pin VCC2 = 8.75V 25 mA
ZIN Internal Differential Impedance 95 105 Ω
ZLINE Line Differential Impedance (PWB or Trace) 90 100 110 Ω
CI Input capacitance(1) f = 1 MHz 10 pF
CO Output capacitance(1) f = 1 MHz 10 pF
CIM Input capacitance for MBRST[0:15] pins f = 1 MHz 160 210 pF
(1) Applies to LVCMOS pins only
(2) Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw. (Refer to Absolute Maximum Ratings for details)
DLP5500 measurementcond_lps013.gifFigure 2. Measurement Condition for LVCMOS Output