DLPS053B October   2014  – October 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Typical Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
      2. 7.5.2 Numerical Aperture and Stray Light Control
      3. 7.5.3 Pupil Match
      4. 7.5.4 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Requirements
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Mirror Park Sequence Requirements
      1. 9.3.1 DLPC900
      2. 9.3.2 DLPC910
    4. 9.4 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PCB Recommendations
    2. 10.2 Layout Example
      1. 10.2.1 Board Stack and Impedance Requirements
        1. 10.2.1.1 Power Planes
        2. 10.2.1.2 LVDS Signals
        3. 10.2.1.3 Critical Signals
        4. 10.2.1.4 Device Placement
        5. 10.2.1.5 Device Orientation
        6. 10.2.1.6 Fiducials
  11. 11Device Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • FYE|350
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

FYE Package
350-Pin CPGA
Bottom View
DLP6500 pins_ds_functions.gif

Pin Functions

PIN(1) TYPE
(I/O/P)		 SIGNAL DATA
RATE(2) 		INTERNAL
TERM(3) 		DESCRIPTION TRACE
(mils)(4)
NAME NO.
DATA BUS A
D_AN(0) B14 Input LVDS DDR Differential Data, Negative 494.88
D_AN(1) B15 Input LVDS DDR Differential Data, Negative 486.18
D_AN(2) C16 Input LVDS DDR Differential Data, Negative 495.16
D_AN(3) K24 Input LVDS DDR Differential Data, Negative 485.67
D_AN(4) B18 Input LVDS DDR Differential Data, Negative 494.76
D_AN(5) L24 Input LVDS DDR Differential Data, Negative 490.63
D_AN(6) C19 Input LVDS DDR Differential Data, Negative 495.16
D_AN(7) H24 Input LVDS DDR Differential Data, Negative 485.55
D_AN(8) H23 Input LVDS DDR Differential Data, Negative 495.16
D_AN(9) B25 Input LVDS DDR Differential Data, Negative 485.59
D_AN(10) D24 Input LVDS DDR Differential Data, Negative 495.16
D_AN(11) E25 Input LVDS DDR Differential Data, Negative 495.16
D_AN(12) F25 Input LVDS DDR Differential Data, Negative 490.04
D_AN(13) H25 Input LVDS DDR Differential Data, Negative 485.91
D_AN(14) L25 Input LVDS DDR Differential Data, Negative 495.16
D_AN(15) G24 Input LVDS DDR Differential Data, Negative 495.16
D_AP(0) C14 Input LVDS DDR Differential Data, Positive 494.84
D_AP(1) B16 Input LVDS DDR Differential Data, Positive 486.22
D_AP(2) C17 Input LVDS DDR Differential Data, Positive 494.65
D_AP(3) K23 Input LVDS DDR Differential Data, Positive 488.42
D_AP(4) B19 Input LVDS DDR Differential Data, Positive 495.16
D_AP(5) L23 Input LVDS DDR Differential Data, Positive 490.67
D_AP(6) C20 Input LVDS DDR Differential Data, Positive 498.11
D_AP(7) J24 Input LVDS DDR Differential Data, Positive 486.22
D_AP(8) J23 Input LVDS DDR Differential Data, Positive 495.47
D_AP(9) C25 Input LVDS DDR Differential Data, Positive 485.94
D_AP(10) E24 Input LVDS DDR Differential Data, Positive 495.16
D_AP(11) D25 Input LVDS DDR Differential Data, Positive 494.13
D_AP(12) G25 Input LVDS DDR Differential Data, Positive 488.98
D_AP(13) J25 Input LVDS DDR Differential Data, Positive 492.56
D_AP(14) K25 Input LVDS DDR Differential Data, Positive 495.16
D_AP(15) F24 Input LVDS DDR Differential Data, Positive 495.16
DATA BUS B
D_BN(0) Z14 Input LVDS DDR Differential Data, Negative 494.92
D_BN(1) Z15 Input LVDS DDR Differential Data, Negative 486.18
D_BN(2) Y16 Input LVDS DDR Differential Data, Negative 496.46
D_BN(3) P24 Input LVDS DDR Differential Data, Negative 493.74
D_BN(4) Z18 Input LVDS DDR Differential Data, Negative 494.76
D_BN(5) N24 Input LVDS DDR Differential Data, Negative 495.16
D_BN(6) Y19 Input LVDS DDR Differential Data, Negative 492.16
D_BN(7) T24 Input LVDS DDR Differential Data, Negative 492.68
D_BN(8) T23 Input LVDS DDR Differential Data, Negative 484.45
D_BN(9) Z25 Input LVDS DDR Differential Data, Negative 492.09
D_BN(10) X24 Input LVDS DDR Differential Data, Negative 497.72
D_BN(11) W25 Input LVDS DDR Differential Data, Negative 495.16
D_BN(12) V25 Input LVDS DDR Differential Data, Negative 484.17
D_BN(13) T25 Input LVDS DDR Differential Data, Negative 481.42
D_BN(14) N25 Input LVDS DDR Differential Data, Negative 495.16
D_BN(15) U24 Input LVDS DDR Differential Data, Negative 489.8
D_BP(0) Y14 Input LVDS DDR Differential Data, Positive 494.88
D_BP(1) Z16 Input LVDS DDR Differential Data, Positive 486.26
D_BP(2) Y17 Input LVDS DDR Differential Data, Positive 495.16
D_BP(3) P23 Input LVDS DDR Differential Data, Positive 492.48
D_BP(4) Z19 Input LVDS DDR Differential Data, Positive 495.16
D_BP(5) N23 Input LVDS DDR Differential Data, Positive 497.99
D_BP(6) Y20 Input LVDS DDR Differential Data, Positive 495.16
D_BP(7) R24 Input LVDS DDR Differential Data, Positive 492.05
D_BP(8) R23 Input LVDS DDR Differential Data, Positive 484.45
D_BP(9) Y25 Input LVDS DDR Differential Data, Positive 492.24
D_BP(10) W24 Input LVDS DDR Differential Data, Positive 495.16
D_BP(11) X25 Input LVDS DDR Differential Data, Positive 494.72
D_BP(12) U25 Input LVDS DDR Differential Data, Positive 483.78
D_BP(13) R25 Input LVDS DDR Differential Data, Positive 489.13
D_BP(14) P25 Input LVDS DDR Differential Data, Positive 499.53
D_BP(15) V24 Input LVDS DDR Differential Data, Positive 488.66
SERIAL CONTROL
SCTRL_AN C23 Input LVDS DDR Differential Serial Control, Negative 492.95
SCTRL_BN Y23 Input LVDS DDR Differential Serial Control, Negative 493.78
SCTRL_AP C24 Input LVDS DDR Differential Serial Control, Positive 493.78
SCTRL_BP Y24 Input LVDS DDR Differential Serial Control, Positive 493.11
CLOCKS
DCLK_AN B23 Input LVDS Differential Clock, Negative 480.35
DCLK_BN Z23 Input LVDS Differential Clock, Negative 486.22
DCLK_AP B22 Input LVDS Differential Clock, Positive 485.83
DCLK_BP Z22 Input LVDS Differential Clock, Positive 491.93
SERIAL COMMUNICATIONS PORT (SCP)
SCP_DO B8 Output LVCMOS SDR Serial Communications Port Output
SCP_DI B7 Input LVCMOS SDR Pull-Down Serial Communications Port Data Input
SCP_CLK B6 Input LVCMOS Pull-Down Serial Communications Port Clock
SCP_ENZ C8 Input LVCMOS Pull-Down Active-low Serial Communications Port Enable
MICROMIRROR RESET CONTROL
RESET_ADDR(0) X9 Input LVCMOS Pull-Down Reset Driver Address Select
RESET_ADDR(1) X8 Input LVCMOS Pull-Down Reset Driver Address Select
RESET_ADDR(2) Z8 Input LVCMOS Pull-Down Reset Driver Address Select
RESET_ADDR(3) Z7 Input LVCMOS Pull-Down Reset Driver Address Select
RESET_MODE(0) W11 Input LVCMOS Pull-Down Reset Driver Mode Select
RESET_MODE(1) Z10 Input LVCMOS Pull-Down Reset Driver Mode Select
RESET_SEL(0) Y10 Input LVCMOS Pull-Down Reset Driver Level Select
RESET_SEL(1) Y9 Input LVCMOS Pull-Down Reset Driver Level Select
RESET_STROBE Y7 Input LVCMOS Pull-Down Reset Address, Mode, & Level latched on rising-edge
ENABLES & INTERRUPTS
PWRDNZ D2 Input LVCMOS Pull-Down Active-low Device Reset
RESET_OEZ W7 Input LVCMOS Pull-Down Active-low output enable for DMD reset driver circuits
RESETZ Z6 Input LVCMOS Pull-Down Active-low sets Reset circuits in known VOFFSET state
RESET_IRQZ Z5 Output LVCMOS Active-low, output interrupt to ASIC
VOLTAGE REGULATOR MONITORING
PG_BIAS E11 Input LVCMOS Pull-Up Active-low fault from external VBIAS regulator
PG_OFFSET B10 Input LVCMOS Pull-Up Active-low fault from external VOFFSET regulator
PG_RESET D11 Input LVCMOS Pull-Up Active-low fault from external VRESET regulator
EN_BIAS D9 Output LVCMOS Active-high enable for external VBIAS regulator
EN_OFFSET C9 Output LVCMOS Active-high enable for external VOFFSET regulator
EN_RESET E9 Output LVCMOS Active-high enable for external VRESET regulator
LEAVE PIN UNCONNECTED
MBRST(0) C2 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(1) C3 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(2) C5 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(3) C4 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(4) E5 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(5) E4 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(6) E3 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(7) G4 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(8) G3 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(9) G2 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(10) J4 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(11) J3 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(12) J2 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(13) L4 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(14) L3 Output Analog Pull-Down For proper DMD operation, do not connect
MBRST(15) L2 Output Analog Pull-Down For proper DMD operation, do not connect
LEAVE PIN UNCONNECTED
RESERVED_PFE E7 Input LVCMOS Pull-Down For proper DMD operation, do not connect
RESERVED_TM D13 Input LVCMOS Pull-Down For proper DMD operation, do not connect
RESERVED_XI1 E13 Input LVCMOS Pull-Down For proper DMD operation, do not connect
RESERVED_TP0 W12 Input Analog For proper DMD operation, do not connect
RESERVED_TP1 Y11 Input Analog For proper DMD operation, do not connect
RESERVED_TP2 X11 Input Analog For proper DMD operation, do not connect
LEAVE PIN UNCONNECTED
RESERVED_BA Y12 Output LVCMOS For proper DMD operation, do not connect
RESERVED_BB C12 Output LVCMOS For proper DMD operation, do not connect
RESERVED_TS D5 Output LVCMOS For proper DMD operation, do not connect
LEAVE PIN UNCONNECTED
NO CONNECT B11 For proper DMD operation, do not connect
NO CONNECT C11 For proper DMD operation, do not connect
NO CONNECT C13 For proper DMD operation, do not connect
NO CONNECT E12 For proper DMD operation, do not connect
NO CONNECT E14 For proper DMD operation, do not connect
NO CONNECT E23 For proper DMD operation, do not connect
NO CONNECT H4 For proper DMD operation, do not connect
NO CONNECT N2 For proper DMD operation, do not connect
NO CONNECT N3 For proper DMD operation, do not connect
NO CONNECT N4 For proper DMD operation, do not connect
NO CONNECT R2 For proper DMD operation, do not connect
NO CONNECT R3 For proper DMD operation, do not connect
NO CONNECT R4 For proper DMD operation, do not connect
NO CONNECT T4 For proper DMD operation, do not connect
NO CONNECT U2 For proper DMD operation, do not connect
NO CONNECT U3 For proper DMD operation, do not connect
NO CONNECT U4 For proper DMD operation, do not connect
NO CONNECT W3 For proper DMD operation, do not connect
NO CONNECT W4 For proper DMD operation, do not connect
NO CONNECT W5 For proper DMD operation, do not connect
NO CONNECT W13 For proper DMD operation, do not connect
NO CONNECT W14 For proper DMD operation, do not connect
NO CONNECT W23 For proper DMD operation, do not connect
NO CONNECT X4 For proper DMD operation, do not connect
NO CONNECT X5 For proper DMD operation, do not connect
NO CONNECT X13 For proper DMD operation, do not connect
NO CONNECT Y2 For proper DMD operation, do not connect
NO CONNECT Y3 For proper DMD operation, do not connect
NO CONNECT Y4 For proper DMD operation, do not connect
NO CONNECT Y5 For proper DMD operation, do not connect
NO CONNECT Z11 For proper DMD operation, do not connect
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected.
(2) DDR = Double Data Rate.
SDR = Single Data Rate.
Refer to the Timing Requirements for specifications and relationships.
(3) Internal term = CMOS level internal termination. Refer to Recommended Operating Conditions for differential termination specification.
(4) Dielectric Constant for the DMD S600 ceramic package is approximately 9.6.
For the package trace lengths shown:
Propagation Speed = 11.8 / sqrt(9.6) = 3.808 in/ns.
Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.

Pin Functions

PIN TYPE
(I/O/P)		 SIGNAL DESCRIPTION
NAME(1) NO.
VBIAS A6, A7, A8, AA6, AA7, AA8 Power Analog Supply voltage for positive Bias level of Micromirror reset signal.
VOFFSET A3, A4, A25 Power Analog Supply voltage for HVCMOS logic.
B26, L26, M26 Power Analog Supply voltage for stepped high voltage at Micromirror address electrodes.
N26, Z26, AA3, AA4 Power Analog Supply voltage for positive Offset level of Micromirror reset signal.
VRESET G1, H1, J1, R1, T1, U1 Power Analog Supply voltage for negative Reset level of Micromirror reset signal.
VCC A9, B3, B5, B12, C1, C6, C10, D4, D6, D8, E1, E2, E10, E15, E16, E17, F3, H2, K1, K3, M4, P1, P3, T2, V3, W1, W2, W6, W9, W10, W15, W16, W17, X3, X6, Y1, Y8, Y13, Z1, Z3, Z12, AA2, AA9, AA10 Power Analog Supply voltage for LVCMOS core logic.
Supply voltage for normal high level at Micromirror address electrodes.
Supply voltage for positive Offset level of Micromirror reset signal during Power Down sequence.
VCCI A16, A17, A18, A20, A21, A23, AA16, AA17, AA18, AA20, AA21, AA23 Power Analog Supply voltage for LVDS receivers.
VSS A5, A10, A11, A19, A22, A24, B2, B4, B9, B13, B17, B20, B21, B24, C7, C15, C18, C21, C22, C26, D1, D3, D7, D10, D12, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D26, E6, E8, E18, E19, E20, E21, E22, E26, F1, F2, F4, F23, F26, G23, G26, H3, H26, J26, K2, K4, K26, L1, M1, M2, M3, M23, M24, M25, N1, P2, P4, P26, R26, T3, T26, U23, U26, V1, V2, V4, V23, V26, W8, W18, W19, W20, W21, W22, W26, X1, X2, X7, X10, X12, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X26, Y6, Y15, Y18, Y21, Y22, Y26, Z2, Z4, Z9, Z13, Z17, Z20, Z21, Z24, AA5, AA11, AA19, AA22, AA24 Power Analog Device Ground. Common return for all power.
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected.