DLPS036B September   2014  – October 2016 DLP9000

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  Capacitance at Recommended Operating Conditions
    9. 7.9  Typical Characteristics
    10. 7.10 System Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Optical and System Image Quality
    14. 7.14 Window Characteristics
    15. 7.15 Chipset Component Usage Specification
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 DLP9000
      2. 9.4.2 DLP9000X
    5. 9.5 Window Characteristics and Optics
      1. 9.5.1 Optical Interface and System Image Quality
      2. 9.5.2 Numerical Aperture and Stray Light Control
      3. 9.5.3 Pupil Match
      4. 9.5.4 Illumination Overfill
    6. 9.6 Micromirror Array Temperature Calculation
    7. 9.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 9.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 9.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 9.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 9.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application using DLP9000
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
      2. 10.2.2 Typical Application Using DLP9000X
  11. 11Power Supply Requirements
    1. 11.1 DMD Power Supply Requirements
    2. 11.2 DMD Power Supply Power-Up Procedure
    3. 11.3 DMD Mirror Park Sequence Requirements
      1. 11.3.1 DLP9000
      2. 11.3.2 DLP9000X
    4. 11.4 DMD Power Supply Power-Down Procedure
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General PCB Recommendations
      2. 12.1.2 Power Planes
      3. 12.1.3 LVDS Signals
      4. 12.1.4 Critical Signals
      5. 12.1.5 Flex Connector Plating
      6. 12.1.6 Device Placement
      7. 12.1.7 Device Orientation
      8. 12.1.8 Fiducials
    2. 12.2 Layout Example
      1. 12.2.1 Board Stack and Impedance Requirements
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Handling
      2. 13.1.2 Device Nomenclature
      3. 13.1.3 Device Markings
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Thermal Characteristics
    2. 14.2 Package Thermal Resistance
    3. 14.3 Case Temperature

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発注情報

12 Layout

12.1 Layout Guidelines

Each chipset provides a solution for many applications including structured light and video projection. This section provides layout guidelines for the DMD.

12.1.1 General PCB Recommendations

The PCB shall be designed to IPC2221 and IPC2222, Class 2, Type Z, at level B producibility and built to IPC6011 and IPC6012, class 2. The PCB board thickness to be 0.062 inches ±10%, using a dielectric material with a low Loss-Tangent, for example: Hitachi 679gs or equivalent.

Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity. Refer to the digital controller data sheets listed under Related Documentation regarding DMD Interface Considerations.

High-speed interface waveform quality and timing on the digital controllers (that is, the LVDS DMD interface) is dependent on the following factors:

  • Total length of the interconnect system
  • Spacing between traces
  • Characteristic impedance
  • Etch losses
  • How well matched the lengths are across the interface

Thus, ensuring positive timing margin requires attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

  • Setup Margin = (controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)
  • Hold-time Margin = (controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)

The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as simultaneously switching output (SSO) noise, crosstalk, and inter-symbol-interference (ISI) noise.

Both the DLPC910 and the DLPC900 I/O timing parameters can be found in their respective data sheets. Similarly, PCB routing mismatch can be easily budgeted and met via controlled PCB routing. However, PCB SI degradation is not as easy to determine.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these recommendations should be confirmed with PCB signal integrity analysis or lab measurements.

12.1.2 Power Planes

Signal routing is NOT allowed on the power and ground planes. All device pin and via connections to this plane shall use a thermal relief with a minimum of four spokes. The power plane shall clear the edge of the PCB by 0.2".

Prior to routing, vias connecting all digital ground layers (GND) should be placed around the edge of the rigid PWB regions 0.025” from the board edges with a 0.100” spacing. It is also desirable to have all internal digital ground (GND) planes connected together in as many places as possible. If possible, all internal ground planes should be connected together with a minimum distance between connections of 0.5". Extra vias are not required if there are sufficient ground vias due to normal ground connections of devices. NOTE: All signal routing and signal vias should be inside the perimeter ring of ground vias.

Power and Ground pins of each component shall be connected to the power and ground planes with one via for each pin. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100”). Unused or spare device pins that are connected to power or ground may be connected together with a single via to power or ground. Ground plane slots are NOT allowed.

Route VOFFSET, VBIAS, and VRESET as a wide trace >20 mils (wider if space allows) with 20 mils spacing.

12.1.3 LVDS Signals

The LVDS signals shall be first. Each pair of differential signals must be routed together at a constant separation such that constant differential impedance (as in section Board Stack and Impedance Requirements) is maintained throughout the length. Avoid sharp turns and layer switching while keeping lengths to a minimum. The distance from one pair of differential signals to another shall be at least 2 times the distance within the pair.

12.1.4 Critical Signals

The critical signals on the board must be hand routed in the order specified below. In case of length matching requirements, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a minimum and the turn angles no sharper than 45 degrees. Avoid routing long trace all around the PCB.

Table 6. Timing Critical Signals

GROUP SIGNAL CONSTRAINTS ROUTING LAYERS
1 D_AP(0:15), D_AN(0:15), DCLK_AP, DCLK_AN, SCTRL_AN, SCTRL_AP, D_BP(0:15), D_BN(0:15), DCLK_BP, DCLK_BN, SCTRL_BN, SCTRL_BP, D_CP(0:15), D_CN(0:15), DCLK_CP, DCLK_CN, SCTRL_CN, SCTRL_CP, D_DP(0:15), D_DN(0:15), DCLK_DP, DCLK_DN, SCTRL_DN, SCTRL_DP. Refer to Table 7 and Table 8 Internal signal layers. Avoid layer switching when routing these signals.
2 RESET_ADDR_(0:3),
RESET_MODE_(0:1),
RESET_OEZ,
RESET_SEL_(0:1)
RESET_STROBE,
RESET_IRQZ. 		Internal signal layers. Top and bottom as required.
3 SCP_CLK, SCP_DO,
SCP_DI, SCP_DMD_CSZ.		 Any
4 Others No matching/length requirement Any

12.1.5 Flex Connector Plating

Plate all the pad area on top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of electrolytic hard gold over a minimum of 150 micro-inches of electrolytic nickel.

12.1.6 Device Placement

Unless otherwise specified, all major components should be placed on top layer. Small components such as ceramic, non-polarized capacitors, resistors and resistor networks can be placed on bottom layer. All high frequency de-coupling capacitors for the ICs shall be placed near the parts. Distribute the capacitors evenly around the IC and locate them as close to the device’s power pins as possible (preferably with no vias). In the case where an IC has multiple de-coupling capacitors with different values, alternate the values of those that are side by side as much as possible and place the smaller value capacitor closer to the device.

12.1.7 Device Orientation

It is desirable to have all polarized capacitors oriented with their positive terminals in the same direction. If polarized capacitors are oriented both horizontally and vertically, then all horizontal capacitors should be oriented with the “+” terminal the same direction and likewise for the vertically oriented ones.

12.1.8 Fiducials

Fiducials for automatic component insertion should be placed on the board according to the following guidelines or on recommendation from manufacturer:

  • Fiducials for optical auto insertion alignment shall be placed on three corners of both sides of the PWB.
  • Fiducials shall also be placed in the center of the land patterns for fine pitch components (lead spacing <0.05").
  • Fiducials should be 0.050 inch copper with 0.100 inch cutout (antipad).

12.2 Layout Example

12.2.1 Board Stack and Impedance Requirements

Refer to Figure 20 regarding guidance on the parameters.

PCB design:
Configuration: Asymmetric dual stripline
Etch thickness (T): 1.0-oz copper (1.2 mil)
Flex etch thickness (T): 0.5-oz copper (0.6 mil)
Single-ended signal impedance: 50 Ω (±10%)
Differential signal impedance: 100 Ω (±10%)
PCB stack-up:
Reference plane 1 is assumed to be a ground plane for proper return path.
Reference plane 2 is assumed to be the I/O power plane or ground.
Dielectric material with a low Loss-Tangent, for example: Hitachi 679gs or equivalent. (Er): 3.8 (nominal)
Signal trace distance to reference plane 1 (H1): 5.0 mil (nominal)
Signal trace distance to reference plane 2 (H2): 34.2 mil (nominal)
DLP9000 PCB_Stack_Geometries.gif Figure 20. PCB Stack Geometries

Table 7. General PCB Routing (Applies to All Corresponding PCB Signals)

PARAMETER APPLICATION SINGLE-ENDED SIGNALS DIFFERENTIAL PAIRS UNIT
Line width (W) Escape routing in ball field 4 .4
(0.1)		 4 .3
(0.1)		 mil
(mm)
PCB etch data or control 7
(0.18)		 4.25
(0.11)		 mil
(mm)
PCB etch clocks 7
(0.18)		 4.25
(0.11)		 mil
(mm)
Differential signal pair spacing (S) PCB etch data or control N/A 5.75 (1)
–0.15		 mil
(mm)
PCB etch clocks N/A 5.75 (1)
–0.15		 mil
(mm)
Minimum differential pair-to-pair spacing (S) PCB etch data or control N/A 20
(0.51)		 mil
(mm)
PCB etch clocks N/A 20
(0.51)		 mil
(mm)
Escape routing in ball field 4
(0.1)		 4
(0.1)		 mil
(mm)
Minimum line spacing to other signals (S) PCB etch data or control 10
(0.25)		 20
(0.51)		 mil
(mm)
PCB etch clocks 20
(0.51)		 20
(0.51)		 mil
(mm)
Maximum differential pair P-to-N length mismatch Total data N/A 10
–0.25		 mil
(mm)
Total data N/A 10
–0.25		 mil
(mm)
(1) Spacing may vary to maintain differential impedance requirements

Table 8. DMD Interface Specific Routing

SIGNAL GROUP LENGTH MATCHING
INTERFACE SIGNAL GROUP REFERENCE SIGNAL MAX MISMATCH UNIT
DMD (LVDS) SCTRL_AN / SCTRL_AP
D_AP(15:0)/ D_AN(15:0) 		DCKA_P/ DCKA_N ± 50
(± 1.3)		 mil
(mm)
DMD (LVDS) SCTRL_BN/ SCTRL_BP
D_BP(15:0)/ D_BN(15:0) 		DCKB_P/ DCKB_N ± 50
(± 1.3)		 mil
(mm)
DMD (LVDS) SCTRL_CN/ SCTRL_CP
D_CP(15:0)/ D_CN(15:0) 		DCK_CP/ DCK_CN ± 50
(± 1.3)		 mil
(mm)
DMD (LVDS) SCTRL_DN/ SCTRL_DP
D_DP(15:0)/ D_DN(15:0) 		DCK_CP/ DCK_CN ± 50
(± 1.3)		 mil
(mm)

Number of layer changes:

  • Single-ended signals: Minimize
  • Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair should not change layers.

Table 9. DMD Signal Routing Length (1)

BUS MIN MAX UNIT
DMD (LVDS) 50 375 mm
(1) Max signal routing length includes escape routing.

Stubs: Stubs should be avoided.

Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100 Ω internally.

Connector (DMD-LVDS interface bus only):

High-speed connectors that meet the following requirements should be used:

  • Differential crosstalk: <5%
  • Differential impedance: 75 to 125 Ω

Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs should be routed in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference for each row should be accounted for on associated PCB etch lengths. Voltage or low frequency signals should be routed on the outer layers. Signal trace corners shall be no sharper than 45 degrees. Adjacent signal layers shall have the predominant traces routed orthogonal to each other.