DLPS033C November   2014  – March 2017 DLP9500UV

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Simplified Schematic
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  LVDS Timing Requirements
    8. 7.8  LVDS Waveform Requirements
    9. 7.9  Serial Control Bus Timing Requirements
    10. 7.10 Systems Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Chipset Component Usage Specification
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      2. 8.3.2 DLPA200 - DMD Micromirror Drivers
      3. 8.3.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
      4. 8.3.4 DLP9500 - DLP 0.95 1080p 2xLVDS UV Type-A DMD 1080p DMD
        1. 8.3.4.1 DLP9500UV 1080p Chipset Interfaces
          1. 8.3.4.1.1 DLPC410 Interface Description
            1. 8.3.4.1.1.1 DLPC410 IO
            2. 8.3.4.1.1.2 Initialization
            3. 8.3.4.1.1.3 DMD Device Detection
            4. 8.3.4.1.1.4 Power Down
          2. 8.3.4.1.2 DLPC410 to DMD Interface
            1. 8.3.4.1.2.1 DLPC410 to DMD IO Description
            2. 8.3.4.1.2.2 Data Flow
          3. 8.3.4.1.3 DLPC410 to DLPA200 Interface
            1. 8.3.4.1.3.1 DLPA200 Operation
            2. 8.3.4.1.3.2 DLPC410 to DLPA200 IO Description
          4. 8.3.4.1.4 DLPA200 to DLP9500UV Interface
            1. 8.3.4.1.4.1 DLPA200 to DLP9500UV Interface Overview
      5. 8.3.5 Measurement Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 Single Block Mode
      2. 8.4.2 Dual Block Mode
      3. 8.4.3 Quad Block Mode
      4. 8.4.4 Global Block Mode
    5. 8.5 Window Characteristics and Optics
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation
    7. 8.7 Micromirror Landed-On and Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DMD Reflectivity Characteristics
        1. 9.1.1.1 Design Considerations Influencing DMD Reflectivity
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Description
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequence (Handled by the DLPC410)
    2. 10.2 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLP9500UV Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Device Marking
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The DLP9500UV devices must be coupled with the DLPC410 controller to provide a reliable solution for many different applications. The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two directions, with the primary direction being into a projection collection optic. Each application is derived primarily from the optical architecture of the system and the format of the data coming into the DLPC410. Applications of interest include 3D printing, lithography, medical systems, and compressive sensing.

DMD Reflectivity Characteristics

TI assumes no responsibility for end-equipment reflectivity performance. Achieving the desired end-equipment reflectivity performance involves making trade-offs between numerous component and system design parameters. Typical DMD reflectivity characteristics over UV exposure times are represented in Figure 18.

DLP9500UV D001_DLPS033.gif
2.3 W/cm2, 363 to 400 nm, 25°C
Figure 18. Nominal DMD Relative Reflectivity Percentage vs Total Exposure Hours

DMD reflectivity includes micromirror surface reflectivity and window transmission. The DMD was characterized for DMD reflectivity using a broadband light source (200-W metal-halide lamp). Data is based off of a 2.3 W/cm2 UV exposure at the DMD surface (365 nm peak output) using a 363 nm high pass filter between the light source and the DMD. (Contact your local Texas Instruments representative for additional information about power density measurements and UV filter details.)

Design Considerations Influencing DMD Reflectivity

Optimal, long-term performance of the digital micromirror device (DMD) can be affected by various application parameters. The following is a list of some of these application parameters and includes high level design recommendations that may help extend relative reflectivity from time zero:

  • Illumination spectrum – using longer wavelengths for operation while preventing shorter wavelengths from striking the DMD
  • Illumination power density – using lower power density
  • DMD case temperature – operating the DMD with the case temperature at the low end of its specification
  • Cumulative incident illumination – Limiting the total hours of UV illumination exposure when the DMD is not actively steering UV light in the application. For example, a design might include a shutter to block the illumination or LED illumination where the LEDs can be strobed off during periods not requiring UV exposure.
  • Micromirror landed duty cycle – applying a 50/50 duty cycle pattern during periods where operational patterns are not required.

Typical Application

The DLP9500UV DMD is designed with a window which allows transmission of ultraviolet (UV) light. This makes it well suited for UV applications requiring fast, spatially programmable light patterns using the micromirror array. UV wavelengths can affect the DMD differently than visible wavelengths. There are system level considerations which should be leveraged when designing systems using this DMD.

DLP9500UV D4100_system_Block_Diag_1080p_update.gif Figure 19. DLPC410 and DLP9500UV Embedded Example Block Diagram

Design Requirements

All applications using the DLP9500UV chipset require both the controller and the DMD components for operation. The system also requires an external parallel flash memory device loaded with the DLPC410 configuration and support firmware. The chipset has several system interfaces and requires some support circuitry. The following interfaces and support circuitry are required:

  • DLPC410 system interfaces:
    • Control interface
    • Trigger interface
    • Input data interface
    • Illumination interface
    • Reference clock
    • Program interface
  • DLP9500UV interfaces:
    • DLPC410 to DLP9500UV digital data
    • DLPC410 to DLP9500UV control interface
    • DLPC410 to DLP9500UV micromirror reset control interface
    • DLPC410 to DLPA200 micromirror driver
    • DLPA200 to DLP9500UV micromirror reset

Device Description

The DLP9500UV 1080p chipset offers developers a convenient way to design a wide variety of industrial, medical, telecom and advanced display applications by delivering maximum flexibility in formatting data, sequencing data, and light patterns.

The DLP9500UV 1080p chipset includes the following four components: DMD digital controller (DLPC410), EEPROM (DLPR410), DMD micromirror driver (DLPA200), and a DMD (DLP9500UV).

DLPC410 Digital Controller for DLP Discovery 4100 chipset

  • Provides high speed 2XLVDS data and control interface to the user
  • Drives mirror clocking pulse and timing information to the DLPA200
  • Supports random row addressing
  • Controls illumination

DLPR410 PROM for DLP Discovery 4100 chipset

  • Contains startup configuration information for the DLPC410

DLPA200 DMD Micromirror Driver

  • Generates micromirror clocking pulse control (sometimes referred to as a reset) of 15 banks of DMD mirrors. (Two are required for the DLP9500UV).

DLP9500UV DLP 0.95 1080p 2xLVDS UV Type-A DMD

  • Steers light in two digital positions (+12° and –12°) using 1920 × 1080 micromirror array of aluminum mirrors.

Table 6. DLP DLP9500UV Chipset Configurations

QUANTITY TI PART DESCRIPTION
1 DLP9500UV DLP 0.95 1080p 2xLVDS UV Type-A DMD
1 DLPC410 Digital Controller for DLP Discovery 4100 chipset
1 DLPR410 PROM for DLP Discovery 4100 chipset
2 DLPA200 DMD Micromirror Driver

Reliable function and operation of DLP9500UV 1080p chipsets require the components be used in conjunction with each other. This document describes the proper integration and use of the DLP9500UV 1080p chipset components.

The DLP9500UV 1080p chipset can be combined with a user programmable application FPGA (not included) to create high performance systems.

Detailed Design Procedure

The DLP9500UV DMD is designed with a window which allows transmission of UV light. This makes it well suited for UV applications requiring fast, spatially programmable light patterns using the micromirror array. UV wavelengths can affect the DMD differently than visible wavelengths. There are system level considerations which should be leveraged when designing systems using this DMD.

Application Curve

DLP9500UV UV_AOI_lps033.gif
Type A UVA on 7056 glass (3 mm thick)
Figure 20. Corning 7056 UV Window Transmittance (Maximum Transmission Region)