DLPS033C November 2014 – March 2017 DLP9500UV
Electrically, the DLP9500UV consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 1920 memory cell columns by 1080 memory cell rows. The CMOS memory array is addressed on a row-by-row basis, over four 16-bit LVDS DDR buses. Addressing is handled by a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital controller.