DLPS033C November 2014 – March 2017 DLP9500UV
Optically, the DLP9500UV consists of 2,073,600 highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors), organized in a two-dimensional array of 1920 micromirror columns by 1080 micromirror rows. Each aluminum micromirror is approximately 10.8 microns in size (see the Micromirror Pitch in Figure 11) and is switchable between two discrete angular positions: –12° and 12°. The angular positions are measured relative to a 0° flat state, which is parallel to the array plane (see Figure 12). The tilt direction is perpendicular to the hinge-axis, which is positioned diagonally relative to the overall array. The On State landed position is directed toward row 0, column 0 (upper left) corner of the device package (see the Micromirror Hinge-Axis Orientation in Figure 11). In the field of visual displays, the 1920 × 1080 pixel resolution is referred to as 1080p.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the mirror clocking pulse is applied. The angular position (–12° or +12°) of the individual micromirrors changes synchronously with a micromirror clocking pulse, rather than being synchronous with the CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking pulse will result in the corresponding micromirror switching to a 12° position. Writing a logic 0 into a memory cell followed by a mirror clocking pulse will result in the corresponding micromirror switching to a –12° position.
Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the CMOS memory. Second, application of a micromirror clocking pulse to all or a portion of the micromirror array (depending upon the configuration of the system). Micromirror clocking pulses are generated externally by two DLPA200s, with application of the pulses being coordinated by the DLPC410 controller.
Around the perimeter of the 1920 by 1080 array of micromirrors is a uniform band of border micromirrors. The border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of the 1920 by 1080 active array.
Figure 7 shows a DLPC410 and DLP9500UV chipset block diagram. The DLPC410 and DLPA200s control and coordinate the data loading and micromirror switching for reliable DLP9500UV operation. The DLPR410 is the programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset components, see Application and Implementation. For a typical system application using the DLP Discovery 4100 chipset including a DLP9500UV, see Figure 19.
Figure 7 shows a simplified system block diagram with the use of the DLPC410 with the following chipset components:
|DMD||ARRAY||SINGLE BLOCK MODE
|GLOBAL RESET MODE
|DLP9500UV - 0.95" 1080p||1920 × 1080||23148 (1)||17857||48||10.8 μm|
The DLPC410 chipset includes the DLPC410 controller which provides a high-speed LVDS data and control interface for DMD control. This interface is also connected to a second FPGA used to drive applications (not included in the chipset). The DLPC410 generates DMD and DLPA200 initialization and control signals in response to the inputs on the control interface.
For more information, see the DLPC410 data sheet (DLPS024).
DLPA200 micromirror drivers provide the micromirror clocking pulse driver functions for the DMD. Two drivers are required for DLP9500UV.
The DLPA200 is designed to work with multiple DLP chipsets. Although the DLPA200 contains 16 MBSRT output pins, only 15 lines are used with the DLP9500 chipset. For more information see and the DLPA200 data sheet (DLPS015).
The DLPC410 controller is configured at startup from the DLPR410 PROM. The contents of this PROM can not be altered. For more information, see the DLPR410 data sheet (DLPS027) the DLPC410 data sheet (DLPS024).
This section will describe the interface between the different components included in the chipset. For more information on component interfacing, see Application and Implementation.
|ARST||Asynchronous active low reset||I|
|CLKIN_R||Reference clock, 50 MHz||I|
|DIN_[A,B,C,D](15:0)||LVDS DDR input for data bus A,B,C,D (15:0)||I|
|DCLKIN[A,B,C,D]||LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and D||I|
|DVALID[A,B,C,D]||LVDS input used to start write sequence for bus A, B, C, and D||I|
|ROWMD(1:0)||DMD row address and row counter control||I|
|ROWAD(10:0)||DMD row address pointer||I|
|BLK_AD(3:0)||DMD mirror block address pointer||I|
|BLK_MD(1:0)||DMD mirror block reset and clear command modes||I|
|PWR_FLOAT||Used to float DMD mirrors before complete loss of power||I|
|DMD_TYPE(3:0)||DMD type in use||O|
|RST_ACTIVE||Indicates DMD mirror reset in progress||O|
|INIT_ACTIVE||Initialization in progress.||O|
|VLED0||System “heartbeat” signal||O|
|VLED1||Denotes initialization complete||O|
The INIT_ACTIVE (Table 2) signal indicates that the DLP9500UV, DLPA200s, and DLPC410 are in an initialization state after power is applied. During this initialization period, the DLPC410 is initializing the DLP9500UV and DLPA200s by setting all internal registers to their correct states. When this signal goes low, the system has completed initialization. System initialization takes approximately 220 ms to complete. Data and command write cycles should not be asserted during the initialization.
During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to correctly align the data inputs to the data clock. For more information, see the interface training pattern information in the DLPC410 data sheet.
The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE (Table 2) is an output from the DLPC410 that contains the DMD information.
To ensure long term reliability of the DLP9500UV, a shutdown procedure must be executed. Prior to power removal, assert the PWR_FLOAT (Table 2) signal and allow approximately 300 µs for the procedure to complete. This procedure assures the mirrors are in a flat state.
Table 3 lists the available controls and status pin names and their corresponding signal type, along with a brief functional description.
|DDC_DOUT_[A,B,C,D](15:0)||LVDS DDR output to DMD data bus A,B,C,D (15:0)||O|
|DDC_DCLKOUT_[A,B,C,D]||LVDS output to DMD data clock A,B,C,D||O|
|DDC_SCTRL_[A,B,C,D]||LVDS DDR output to DMD data control A,B,C,D||O|
Figure 8 shows the data traffic through the DLPC410. Special considerations are necessary when laying out the DLPC410 to allow best signal flow.
Four LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the DLPC410 (DVALID).
Output LVDS buses transfer data from the DLPC410 to the DMD. Output buses LVDS C and LVDS D are used in addition to LVDS A and LVDS B with the DLP9500UV.
The DLPA200 DMD micromirror driver is a mixed-signal application-specific integrated circuit (ASIC) that combines the necessary high-voltage power supply generation and micromirror clocking pulse functions for a family of DMDs. The DLPA200 is programmable and controllable to meet all current and anticipated DMD requirements.
The DLPA200 operates from a 12-V power supply input. For more detailed information on the DLPA200, see the DLPA200 data sheet.
The serial communications port (SCP) is a full duplex, synchronous, character-oriented (byte) port that allows exchange of commands from the DLPC410 to the DLPA200s.
Five signal lines are associated with the SCP bus: SCPEN, SCPCK, SCPDI, SCPDO, and IRQ.
Table 4 lists the available controls and status pin names and their corresponding signal type, along with a brief functional description.
|A_SCPEN||Active-low chip select for DLPA200 serial bus||O|
|A_STROBE||DLPA200 control signal strobe||O|
|A_MODE(1:0)||DLPA200 mode control||O|
|A_SEL(1:0)||DLPA200 select control||O|
|A_ADDR(3:0)||DLPA200 address control||O|
|B_SCPEN||Active-low chip select for DLPA200 serial bus (2)||O|
|B_STROBE||DLPA200 control signal strobe (2)||O|
|B_MODE(1:0)||DLPA200 mode control||O|
|B_SEL(1:0)||DLPA200 select control||O|
|B_ADDR(3:0)||DLPA200 address control||O|
The DLPA200 provides a variety of output options to the DMD by selecting logic control inputs: MODE[1:0], SEL[1:0] and reset group address A[3:0] (Table 4). The MODE[1:0] input determines whether a single output, two outputs, four outputs, or all outputs, will be selected. Output levels (VBIAS, VOFFSET, or VRESET) are selected by SEL[1:0] pins. Selected outputs are tri-stated on the rising edge of the STROBE signal and latched to the selected voltage level after a break-before-make delay. Outputs will remain latched at the last micromirror clocking pulse waveform level until the next micromirror clocking pulse waveform cycle.
The DLPA200 generates three voltages: VBIAS, VRESET, and VOFFSET that are supplied to the DMD MBRST lines in various sequences through the micromirror clocking pulse driver function. VOFFSET is also supplied directly to the DMD as DMDVCC2. A fourth DMD power supply, DMDVCC, is supplied directly to the DMD by regulators.
The function of the micromirror clocking pulse driver is to switch selected outputs in patterns between the three voltage levels (VBIAS, VRESET and VOFFSET) to generate one of several micromirror clocking pulse waveforms. The order of these micromirror clocking pulse waveform events is controlled externally by the logic control inputs and timed by the STROBE signal. DLPC410 automatically detects the DMD type and then uses the DMD type to determine the appropriate micromirror clocking pulse waveform.
A direct micromirror clocking pulse operation causes a mirror to transition directly from one latched state to the next. The address must already be set up on the mirror electrodes when the micromirror clocking pulse is initiated. Where the desired mirror display period does not allow for time to set up the address, a micromirror clocking pulse with release can be performed. This operation allows the mirror to go to a relaxed state regardless of the address while a new address is set up, after which the mirror can be driven to a new latched state.
A mirror in the relaxed state typically reflects light into a system collection aperture and can be thought of as off although the light is likely to be more than a mirror latched in the off state. System designers should carefully evaluate the impact of relaxed mirror conditions on optical performance.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. Figure 10 shows an equivalent test load circuit for the output under test. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks.
The DLP9500UV has only one functional mode; it is set to be highly optimized for low latency and high speed in generating mirror clocking pulses and timings.
When operated with the DLPC410 controller in conjunction with the DLPA200 drivers, the DLP9500UV can be operated in several display modes. The DLP9500UV is loaded as 15 blocks of 72 rows each. The first 64 bits of pixel data and last 64 bits of pixel data for all rows are not visible. Below is a representation of how the image is loaded by the different micromirror clocking pulse modes. Figure 13, Figure 14, Figure 15, and Figure 16 show how the image is loaded by the different micromirror clocking pulse modes.
There are four micromirror clocking pulse modes that determine which blocks are reset when a micromirror clocking pulse command is issued:
In single block mode, a single block can be loaded and reset in any order. After a block is loaded, it can be reset to transfer the information to the mechanical state of the mirrors.
In dual block mode, reset blocks are paired together as follows (0-1), (2-3), (4-5), (6-7), (8-9), (10-11), (12-13), and (14). These pairs can be reset in any order. After data is loaded a pair can be reset to transfer the information to the mechanical state of the mirrors.
In quad block mode, reset blocks are grouped together in fours as follows (0-3), (4-7), (8-11) and (12-14). Each quad group can be randomly addressed and reset. After a quad group is loaded, it can be reset to transfer the information to the mechanical state of the mirrors.
In global mode, all reset blocks are grouped into a single group and reset together. The entire DMD must be loaded with the desired data before issuing a Global Reset to transfer the information to the mechanical state of the mirrors.
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously.
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in the following sections.
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination, projection pupils, or both to block out flat-state and stray light from the projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
TI recommends the exit pupil of the illumination is nominally centered within 2° (two degrees) of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active area, which may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the average flux level in the active area. Depending on the optical architecture of a particular system, overfill light may have to be further reduced below the suggested 10% level to be acceptable.
Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the maximum temperature of any individual micromirror in the active array, the maximum temperature of the window aperture, and the temperature gradient between case temperature and the predicted micromirror array temperature (see Figure 17).
See the Recommended Operating Conditions for applicable temperature limits.
The DMD is designed to conduct absorbed and dissipated heat to the back of the type A package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the specified operational temperatures, refer to Figure 17. The total heat load on the DMD is typically driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array.
The temperature of the DMD case can be measured directly. For consistency, thermal test point locations 1, 2, and 3 are defined, as shown in Figure 17.
Active array temperature cannot be measured directly; therefore, it must be computed analytically from measurement points on the outside of the package, package thermal resistance, electrical power, and illumination heat load. The relationship between array temperature and the reference ceramic temperature (test point number 1 in Figure 17) is provided by the following equations:
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating frequencies. The nominal electrical power dissipation of the DMD is variable and depends on the operating state of mirrors and the intensity of the light source. The DMD absorption constant of 0.42 assumes nominal operation with an illumination distribution of 83.7% on the active array, 11.9% on the array border, and 4.4% on the window aperture. A system aperture may be required to limit power incident on the package aperture since this area absorbs much more efficiently than the array.
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the On–state versus the amount of time the same micromirror is landed in the Off–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state (OFF or ON) is considered negligible and is thus ignored.
Because a micromirror can only be landed in one state or the other (on or off), the two numbers (percentages) always add to 100.
Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed duty cycle for a prolonged period of time can reduce the usable life of the DMD.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical.
Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD, and this interaction can be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD’s usable life.
In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at for a give long-term average landed duty.
During a given period of time, the landed duty cycle of a given pixel follows from the image content being displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel will experience a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the pixel will experience a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in Table 5.
|GRAYSCALE VALUE||LANDED DUTY CYCLE|