DLPS033C November 2014 – March 2017 DLP9500UV
The DLP9500UV is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These guidelines are targeted at designing a PCB board with these components.
Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs (DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn) which should be matched to 100 Ω ±10% across each pair.
When designing a PCB board for the DLP9500UV controlled by the DLPC410 in conjunction with the DLPA200s, the following are recommended:
Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2 Memory, DMD (LVDS signals), then DLPA200 signals.
TI does not recommend signal routing on power or ground planes.
TI does not recommend ground plane slots.
High speed signal traces should not cross over slots in adjacent power and/or ground planes.
DMD_DCKL_xn, and DMD_SCTRL_xn)
|P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle <2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn)
Trace width: 4 mil (0.1 mm)
Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)
Maximum recommended trace length <6 inches (150 mm)
|SIGNAL NAME||MINIMUM TRACE WIDTH||MINIMUM TRACE SPACING||LAYOUT REQUIREMENTS|
|GND||Maximize||5 mil (0.13 mm)||Maximize trace width to connecting pin as a minimum|
|VCC, VCC2||20 mil (0.51 mm)||10 mil (0.25 mm)|
|MBRST[14:0]||11 mil (0.28 mm)||15 mil (0.38 mm)|
Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials for optical auto insertion are placed on three corners of both sides of the PCB.
A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals is specified for all signal layers.
The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. The LVDS signals should have 100 Ω differential impedance. The differential signals should be matched but kept as short as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is not necessary.
The DLPC410 DMD data signals require precise length matching. Differential signals should have impedance of 100 Ω (with 5% tolerance). It is important that the propagation delays are matched. The maximum differential pair uncoupled length is 100 mils with a relative propagation delay of ±25 mil between the p and n. Matching all signals exactly will maximize the channel margin. The signal path through all boards, flex cables and internal DMD routing must be considered in this calculation.
General decoupling capacitors for the DLP9500UV should be distributed around the PCB and placed to minimize the distance from IC voltage and ground pads. Each decoupling capacitor (0.1 µF recommended) should have vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is discouraged. The power and ground pads of the DLP9500UV should be tied to the voltage and ground planes with their own vias.
Decoupling capacitors should be placed to minimize the distance from the decoupling capacitor to the supply and ground pin of the component. TI recommends that the placement of and routing for the decoupling capacitors meet the following guidelines:
The VCC pins of the DMD should be connected directly to the DMD VCC plane. Decoupling for the VCC should be distributed around the DMD and placed to minimize the distance from the voltage and ground pads. Each decoupling capacitor should have vias directly connected to the ground and power planes. The VCC and GND pads of the DMD should be tied to the VCC and ground planes with their own vias.
The VCC2 voltage can be routed to the DMD as a trace. Decoupling capacitors should be placed to minimize the distance from the DMD’s VCC2 and ground pads. Using wide etch from the decoupling capacitors to the DMD connection will reduce inductance and improve decoupling performance.
See the respective sections in this data sheet for package dimensions, timing and pin out information.
The DLPA200 generates the micromirror clocking pulses for the DMD. The DMD-drive outputs from the DLPA200 (MBRST[29:0] should be routed with minimum trace width of 11 mil and a minimum spacing of 15 mil. The VCC and VCC2 traces from the output capacitors to the DLPA200 should also be routed with a minimum trace width and spacing of 11 mil and 15 mil, respectively. See the DLPA200 customer data sheet DLPS015 for mechanical package and layout information.
For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the dashed lines, Figure 21 shows correct matching of signal pair lengths with serpentine sections to maintain the correct impedance.