DLPS033C November   2014  – March 2017 DLP9500UV

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Simplified Schematic
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  LVDS Timing Requirements
    8. 7.8  LVDS Waveform Requirements
    9. 7.9  Serial Control Bus Timing Requirements
    10. 7.10 Systems Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Chipset Component Usage Specification
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      2. 8.3.2 DLPA200 - DMD Micromirror Drivers
      3. 8.3.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
      4. 8.3.4 DLP9500 - DLP 0.95 1080p 2xLVDS UV Type-A DMD 1080p DMD
        1. 8.3.4.1 DLP9500UV 1080p Chipset Interfaces
          1. 8.3.4.1.1 DLPC410 Interface Description
            1. 8.3.4.1.1.1 DLPC410 IO
            2. 8.3.4.1.1.2 Initialization
            3. 8.3.4.1.1.3 DMD Device Detection
            4. 8.3.4.1.1.4 Power Down
          2. 8.3.4.1.2 DLPC410 to DMD Interface
            1. 8.3.4.1.2.1 DLPC410 to DMD IO Description
            2. 8.3.4.1.2.2 Data Flow
          3. 8.3.4.1.3 DLPC410 to DLPA200 Interface
            1. 8.3.4.1.3.1 DLPA200 Operation
            2. 8.3.4.1.3.2 DLPC410 to DLPA200 IO Description
          4. 8.3.4.1.4 DLPA200 to DLP9500UV Interface
            1. 8.3.4.1.4.1 DLPA200 to DLP9500UV Interface Overview
      5. 8.3.5 Measurement Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 Single Block Mode
      2. 8.4.2 Dual Block Mode
      3. 8.4.3 Quad Block Mode
      4. 8.4.4 Global Block Mode
    5. 8.5 Window Characteristics and Optics
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation
    7. 8.7 Micromirror Landed-On and Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DMD Reflectivity Characteristics
        1. 9.1.1.1 Design Considerations Influencing DMD Reflectivity
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Description
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequence (Handled by the DLPC410)
    2. 10.2 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLP9500UV Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Device Marking
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Specifications

Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted). (1)
MIN MAX UNIT
ELECTRICAL
VCC Voltage applied to VCC (2) (3) –0.5 4 V
VCCI Voltage applied to VCCI (2) (3) –0.5 4 V
VCC2 Voltage applied to VVCC2 (2) (3) (4) –0.5 9 V
VMBRST Clocking pulse waveform voltage applied to MBRST[29:0] input pins (supplied by DLPA200s) –28 28 V
|VCC – VCCI| Supply voltage delta (absolute value) (4) 0.3 V
Voltage applied to all other input terminals (2) –0.5 VCC + 0.3 V
|VID| Maximum differential voltage, damage can occur to internal termination resistor if exceeded, see Figure 2 700 mV
Current required from a high-level output, VOH = 2.4 V –20 mA
Current required from a low-level output, VOL = 0.4 V 15 mA
ENVIRONMENTAL
TC Case temperature – operational (5) 20 30 °C
Case temperature – non-operational (5) –40 80 °C
TGRADIENT Device temperature gradient – operational (6) 10 °C
RH Relative humidity (non-condensing) 95 %RH
Stresses beyond those listed under Recommended Operating Conditions may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS (ground).
Voltages VCC, VCCI, and VCC2 are required for proper DMD operation.
Exceeding the recommended allowable absolute voltage difference between VCC and VCCI may result in excess current draw. The difference between VCC and VCCI, |VCC – VCCI|, should be less than the specified limit.
DMD Temperature is the worst-case of any test point shown in Case Temperature, or the active array as calculated by the Micromirror Array Temperature Calculation.
As either measured, predicted, or both between any two points - measured on the exterior of the package, or as predicted at any point inside the micromirror array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.

Storage Conditions

applicable before the DMD is installed in the final product
MIN MAX UNIT
TDMD Storage temperature –40 80 °C
RH Storage humidity (non-condensing) 95 %RH

ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) All pins except MBRST[29:0] ±2000 V
MBRST[29:0] pins ±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted). (1)
MIN NOM MAX UNIT
ELECTRICAL
VCC LVCMOS interface supply voltage (9) (2) 3 3.3 3.6 V
VCCI LVCMOS logic supply voltage (9) (2) 3 3.3 3.6 V
VCC2 Mirror electrode and HVCMOS supply voltage (9) (2) 8.25 8.5 8.75 V
VMBRST Clocking pulse waveform voltage applied to MBRST[29:0] input pins (supplied by DLPA200s) –27 26.5 V
MECHANICAL
Static load applied to electrical interface area, see (7) Figure 5 1334 N
Static load applied to the thermal interface area, see (8) Figure 5 156 N
Static load applied to Datum 'A' interface area Figure 5 712 N
ENVIRONMENTAL (3)
Illumination power density (11) < 363 nm (12) 2 mW/cm2
363 to 400 nm(13) 2.5 W/cm2
6 W
400 to 420 nm (13) 11 W/cm2
26.6 W
363 to 420 nm total (13) (14) 11 W/cm2
26.6 W
> 420 nm Thermally limited (13) W/cm2
TC Case/Array Temperature (4) (16) 20 30(5) °C
TGRADIENT Device temperature gradient (6) 10 °C
RH Relative humidity (non-condensing) (10) 95 %RH
Operating landed duty cycle (15) 25%
The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.
Voltages VCC, VCC2, and VCCI,are required for proper DMD operation. VSS must also be connected.
Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.
In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See Micromirror Array Temperature Calculation for further details.
See the Micromirror Array Temperature Calculation for thermal test point locations, package thermal resistance, and device temperature calculation.
As either measured, predicted, or both between any two points - measured on the exterior of the package, or as predicted at any point inside the micromirror array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.
Load should be uniformly distributed across the entire electrical interface area.
Load should be uniformly distributed across thermal interface area. Refer to Figure 5.
All voltages referenced to VSS (ground).
Various application parameters can affect optimal, long-term performance of the DMD, including illumination spectrum, illumination power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case temperature, and power-on or power-off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle. Contact your local TI representative for additional information related to optimizing the DMD performance.
Total integrated illumination power density, above or below the indicated wavelength threshold or in the indicated wavelength range.
The maximum operating conditions for operating temperature and illumination power density for wavelengths < 363nm should not be implemented simultaneously.
Also limited by the resulting micromirror array temperature. Refer to Case Temperature and Micromirror Array Temperature Calculation for information related to calculating the micromirror array temperature.
The total integrated illumination power density from 363 to 420 nm shall not exceed 11 W/cm2 (or 26.6 W evenly distributed on the active array area). Therefore if 2.5 W/cm2 of illumination is used in the 363 to 400 nm range, then illumination in the 400 to 420 nm range must be limited to 8.5 W/cm2.
Landed duty cycle refers to the percentage of time an individual micromirror spends landed in one state (12° or –12°) versus the other state (–12° or 12°).
Temperature is the highest measured value of any test point shown in Figure 17 or the active array as calculated by the Micromirror Array Temperature Calculation.

Thermal Information

THERMAL METRIC (2) (1) DLP9500UV UNIT
FLN (LCCC)
355 PINS
Active micromirror array resistance to TP1 0.5 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

Electrical Characteristics

over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted); under recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage (1),
See Figure 10
VCC = 3 V, IOH = –20 mA 2.4 V
VOL Low-level output voltage (1),
See Figure 10
VCC = 3.6 V, IOH = 15 mA 0.4 V
VMBRST Clocking pulse waveform applied to MBRST[29:0] input pins (supplied by DLPA200s) –27 26.5 V
IOZ High-impedance output current (1) VCC = 3.6 V 10 µA
IOH High-level output current (1) VOH = 2.4 V, VCC ≥ 3 V –20 mA
VOH = 1.7 V, VCC ≥ 2.25 V –15
IOL Low-level output current (1) VOL = 0.4 V, VCC ≥ 3 V 15 mA
VOL = 0.4 V, VCC ≥ 2.25 V 14
VIH High-level input voltage (1) 1.7 VCC + 0.3 V
VIL Low-level input voltage (1) –0.3 0.7 V
IIL Low-level input current (1) VCC = 3.6 V, VI = 0 V –60 µA
IIH High-level input current (1) VCC = 3.6 V, VI = VCC 60 µA
ICC Current into VCC pin VCC = 3.6 V, 2990 mA
ICCI Current into VOFFSET pin (2) VCCI = 3.6 V 910 mA
ICC2 Current into VCC2 pin VCC2 = 8.75 V 25 mA
PD Power dissipation 4.4 W
ZIN Internal differential impedance 95 105 Ω
ZLINE Line differential impedance (PWB, trace) 90 100 110 Ω
CI Input capacitance (1) ƒ = 1 MHz 10 pF
CO Output capacitance (1) ƒ = 1 MHz 10 pF
CIM Input capacitance for MBRST[29:0] pins ƒ = 1 MHz 270 355 pF
Applies to LVCMOS pins only.
Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw (See Absolute Maximum Ratings for details).

LVDS Timing Requirements

over operating free-air temperature range (unless otherwise noted); see Figure 1
MIN NOM MAX UNIT
ƒDCLK_x DCLK_x clock frequency (where x = [A, B, C, or D]) 200 400 MHz
tc Clock cycle - DLCK_x 2.5 ns
tw Pulse duration - DLCK_x 1.25 ns
ts Setup time - D_x[15:0] and SCTRL_x before DCLK_x 0.35 ns
th Hold time, D_x[15:0] and SCTRL_x after DCLK_x 0.35 ns
tskew Skew between any two buses (A ,B, C, and D) –1.25 1.25 ns
DLP9500UV LVDS_timing_lps025.gif Figure 1. LVDS Timing Waveforms

LVDS Waveform Requirements

over operating free-air temperature range (unless otherwise noted); see Figure 2
MIN NOM MAX UNIT
|VID| Input differential voltage (absolute difference) 100 400 600 mV
VCM Common mode voltage 1200 mV
VLVDS LVDS voltage 0 2000 mV
tr Rise time (20% to 80%) 100 400 ps
tr Fall time (80% to 20%) 100 400 ps
DLP9500UV LVDS_waveform_requir_lps025.gif Figure 2. LVDS Waveform Requirements

Serial Control Bus Timing Requirements

over operating free-air temperature range (unless otherwise noted); see Figure 3 and Figure 4
MIN NOM MAX UNIT
ƒSCP_CLK SCP clock frequency 50 500 kHz
tSCP_SKEW Time between valid SCP_DI and rising edge of SCP_CLK –300 300 ns
tSCP_DELAY Time between valid SCP_DO and rising edge of SCP_CLK 960 ns
t SCP_EN Time between falling edge of SCP_EN and the first rising edge of SCP_CLK 30 ns
t_SCP Rise time for SCP signals 200 ns
tƒ_SCP Fall time for SCP signals 200 ns
DLP9500UV SCP_Timing_Parameters.gif Figure 3. Serial Communications Bus Timing Parameters
DLP9500UV inputrisefall_cmos_lps013.gif Figure 4. Serial Communications Bus Waveform Requirements

Systems Mounting Interface Loads

PARAMETER MIN NOM MAX UNIT
Maximum system mounting interface load to be applied to the: Thermal interface area (see Figure 5) 156 N
Electrical interface area (see Figure 5) 1334 N
Datum A Interface area (see Figure 5) 712 N
DLP9500UV system_mounting_update_.gif Figure 5. System Interface Loads

Micromirror Array Physical Characteristics

See Mechanical, Packaging, and Orderable Information for additional details.
VALUE UNIT
M Number of active micromirror columns (1) 1920 micromirrors
N Number of active micromirror rows (1) 1080 micromirrors
P Micromirror (pixel) pitch (1) 10.8 µm
Micromirror active array width (1) M × P 20.736 mm
Micromirror active array height (1) N × P 11.664 mm
Micromirror array border (1) (2) Pond of micromirrors (POM) 10 micromirrors/side
See Figure 6.
The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF.
DLP9500UV Micromirror_Array_Physical.gif
Refer to the Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 6. Micromirror Array Physical Characteristics

Micromirror Array Optical Characteristics

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. See the related application reports (listed in Related Documentation) for guidelines.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
a Micromirror tilt angle DMD parked state (1) (2) (3), See Figure 12 0 degrees
DMD landed state (1) (4) (5)
See Figure 12
12
β Micromirror tilt angle variation (1) (4) (6) (7) (8) See Figure 12 –1 1 degrees
Micromirror crossover time (9) 3 µs
Micromirror switching time (10) 13 22 µs
Array switching time at 400 MHz with global reset (11) 56 µs
Non-operating micromirrors (12) Non-adjacent micromirrors 10 micromirrors
Adjacent micromirrors 0
Orientation of the micromirror axis-of-rotation (13) See Figure 12 44 45 46 degrees
Micromirror array optical efficiency (14) (15) 363 to 420 nm, with all micromirrors in the ON state 68%
Window material Corning 7056
Window artifact size Within the window aperture (17) 400 µm
Window aperture See (16)
Measured relative to the plane formed by the overall micromirror array.
Parking the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by the overall micromirror array).
When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled.
Additional variation exists between the micromirror array and the package datums, as shown in Mechanical, Packaging, and Orderable Information.
When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in an nominal angular position of +12°. A binary value of 0 results in a micromirror landing in an nominal angular position of –12°.
Represents the landed tilt angle variation relative to the nominal landed tilt angle.
Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices.
For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in colorimetry variations and/or system contrast variation.
Micromirror crossover time is the transition time from landed to landed during a crossover transition and primarily a function of the natural response time of the micromirrors.
Micromirror switching time is the time after a micromirror clocking pulse until the micromirrors can be addressed again. It included the micromirror settling time.
Array switching is controlled and coordinated by the DLPC410 (DLPS024) and DLPA200 (DLPS015). Nominal switching time depends on the system implementation and represents the time for the entire micromirror array to be refreshed (array loaded plus reset and mirror settling time).
Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12° position to +12° or vice versa.
Measured relative to the package datums 'B' and 'C', shown in the Mechanical, Packaging, and Orderable Information.
The minimum or maximum DMD optical efficiency observed in a specific application depends on numerous application-specific design variables, such as:
  • Illumination wavelength, bandwidth/line-width, degree of coherence
  • Illumination angle, plus angle tolerance
  • Illumination and projection aperture size, and location in the system optical path
  • Illumination overfill of the DMD micromirror array
  • Aberrations present in the illumination source and/or path
  • Aberrations present in the projection path

The specified nominal DMD optical efficiency is based on the following use conditions:
  • UV illumination (363 to 420 nm)
  • Input illumination optical axis oriented at 24° relative to the window normal
  • Projection optical axis oriented at 0° relative to the window normal
  • ƒ / 3.0 illumination aperture
  • ƒ / 2.4 projection aperture

Based on these use conditions, the nominal DMD optical efficiency results from the following four components:
  • Micromirror array fill factor: nominally 92%
  • Micromirror array diffraction efficiency: nominally 85%
  • Micromirror surface reflectivity: nominally 88%
  • Window transmission: nominally 98% (single pass, through two surface transitions)
Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.
See Mechanical, Packaging, and Orderable Information for details regarding the size and location of the window aperture.
Refers only to non-cleanable artifacts. See the DMD S4xx Glass Cleaning Procedure (DLPA025) and DMD S4xx Handling Specifications (DLPA014) for recommended handling and cleaning processes.

Chipset Component Usage Specification

The DLP9500UV is a component of one or more DLP chipsets. Reliable function and operation of the DLP9500UV requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD.