JAJSDU9A February   2017  – May 2017 DLPA1000

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DMD Regulators
      2. 7.3.2 RGB Strobe Decoder
      3. 7.3.3 LED Current Control
        1. 7.3.3.1 LED Current Accuracy
        2. 7.3.3.2 Transient Current Limiting
      4. 7.3.4 Measurement System
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)
        2. 7.3.5.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)
        3. 7.3.5.3 DMD Regulator Fault (DMD_FLT)
        4. 7.3.5.4 V6V Power-Good (V6V_PGF) Fault
        5. 7.3.5.5 VLED Over-Voltage (VLED_OVP) Fault
      6. 7.3.6 Interrupt Pin (INTZ)
      7. 7.3.7 Serial Peripheral Interface (SPI)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Password Protected Registers
    6. 7.6 Register Maps
      1. 7.6.1  Chip ID (CHIPID) Register (address = 0x00h) [reset = A6h]
      2. 7.6.2  Enable (ENABLE) Register (address = 0x01h) [reset = 3h]
      3. 7.6.3  Switch Transient Current Limit (IREG) Register (address = 0x02h) [reset = 28h]
      4. 7.6.4  SW4 LED DC Regulation Current, MSB (SW4MSB) Register (address = 0x03h) [reset = 0h]
      5. 7.6.5  SW4 LED DC Regulation Current, LSB (SW4LSB) Register (address = 0x04h) [reset = 0h]
      6. 7.6.6  SW5 LED DC Regulation Current, MSB (SW5MSB) Register (address = 0x05h) [reset = 0h]
      7. 7.6.7  SW5 LED DC Regulation Current, LSB (SW5LSB) Register (address = 0x06h) [reset = 0h]
      8. 7.6.8  SW6 LED DC Regulation Current, MSB (SW6MSB) Register (address = 0x07h) [reset = 0h]
      9. 7.6.9  SW6 LED DC Regulation Current, LSB (SW6LSB) Register (address = 0x08h) [reset = 0h]
      10. 7.6.10 Analog Front End Control (AFE) Register (address = 0x0Ah) [reset = 0h]
      11. 7.6.11 Strobe Decode - Break Before Make Timing Control (BBM) Register (address = 0x0Bh) [reset = 0h]
      12. 7.6.12 Interrupt (INT) Register (address = 0x0Ch) [reset = X]
      13. 7.6.13 Interrupt Mask (MASK) Register (address = 0x0Dh) [reset = 0h]
      14. 7.6.14 Password (PASSWORD) Register (address = 0x10h) [reset = 0h]
      15. 7.6.15 System Configuration (SYSTEM) Register (address = 0x11h) [reset = 0h]
      16. 7.6.16 EEPROM User Register, Byte0 (BYTE0) (address = 0x20h) [reset = 0h]
      17. 7.6.17 EEPROM User Register, Byte1 (BYTE1) (address = 0x21h) [reset = 0h]
      18. 7.6.18 EEPROM User Register, Byte2 (BYTE2) (address = 0x22h) [reset = 0h]
      19. 7.6.19 EEPROM User Register, Byte3 (BYTE3) (address = 0x23h) [reset = 0h]
      20. 7.6.20 EEPROM User Register, Byte4 (BYTE4) (address = 0x24h) [reset = 0h]
      21. 7.6.21 EEPROM User Register, Byte5 (BYTE5) (address = 0x25h) [reset = 0h]
      22. 7.6.22 EEPROM User Register, Byte6 (BYTE6) (address = 0x26h) [reset = 0h]
      23. 7.6.23 EEPROM User Register, Byte7 (BYTE7) (address = 0x27h) [reset = 0h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VLED Buck-Boost
          1. 8.2.2.1.1 Calculating Inductor Peak Current
        2. 8.2.2.2 DMD Supplies
        3. 8.2.2.3 LDOs and Digital Logic
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • YFF|49
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Input voltage VINL, VINA, VINR –0.3 7 V
Ground pins to system ground –0.3 0.3 V
Voltage SWN –18 7 V
SWP, VBIAS –0.3 20
VOFS –0.3 10
V6V, VLED, L1, L2, SW1, SW2, SW3, SW4, SW5, SW6, INTZ, PROJ_ON –0.3 7
All pins unless noted otherwise –0.3 3.6 V
Source current RESETZ, PWR_EN, CMP_OUT 1 mA
SPI_DOUT 5.5
Sink current RESETZ, PWR_EN, CMP_OUT 1 mA
SPI_DOUT, INTZ 5.5
Peak output current Internally limited mA
Continuous total power dissipation Internally limited W
TA Operating ambient temperature –30 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage at VINL, VINA, VINR Full functional and parametric performance 2.7 3.6 6 V
Extended operation, limited parametric performance 2.3 3.6 6
Voltage at VSPI 1.7 1.8 3.6 V
TA Operating ambient temperature –10 85 °C
TJ Operating junction temperature –10 125 °C

6.4 Thermal Information

THERMAL METRIC(1) DLPA1000 UNIT
YFF (DSBGA)
49 PINS
RθJA Junction-to-ambient thermal resistance 49 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.1 °C/W
RθJB Junction-to-board thermal resistance 6.9 °C/W
ψJT Junction-to-top characterization parameter 1.1 °C/W
ψJB Junction-to-board characterization parameter 6.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

VIN = 3.6 V, TA = –10°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE
VIN Input voltage range VINA, VINR, VINL 2.7 3.6 6 V
Extended input voltage range(1) 2.3 3.6 6
VLOW_BAT Low battery warning threshold VINA falling 3 V
Hysteresis VINA rising 100 mV
VUVLO Undervoltage lockout threshold VINA falling 2.3 V
Hysteresis VINA rising 100 mV
VSTARTUP Startup voltage VBIAS, VOFS, VRST loaded with 2 mA 2.5 V
INPUT CURRENT
IQ ACTIVE2 mode 12 mA
ISTD STANDBY mode 360 µA
ISLEEP SLEEP mode 10 µA
INTERNAL SUPPLIES
VV6V Internal supply, analog 6.25 V
CLDO_V6V Filter capacitor for V6V LDO 100 nF
VV2V5 Internal supply, logic 2.5 V
CLDO_V2V5 Filter capacitor for V2V5 LDO 2.2 µF
DMD REGULATOR
RDS(ON) MOSFET on resistance Switch E (from VINR to SWN) 1000 mΩ
Switch F (from SWP to PGND) 320
VFW Forward voltage drop Switch G (from SWP to VBIAS)(2)
VINR = 5 V, VSWP = 2 V, IF = 100 mA 		1.3 V
Switch H (from SWP to VOFS)
VINR = 5 V, VSWP = 2 V, IF = 100 mA 		1.3
RDIS Discharge resistor (SWP to GND) Active when all rails are disabled 2 kΩ
tPG Power-good timeout Not tested in production 6 ms
ILIMIT Switch current limit 200(3) mA
L Inductor value 10 µH
VOFS REGULATOR
VOFS Output voltage 8.5 V
DC output voltage accuracy IOUT = 2 mA –2% 2%
DC load regulation VIN = 3.6 V, IOUT= 0 mA to 4 mA –19 V/A
DC line regulation VINA, VINL, VINR 2.7 V to 6 V,
IOUT = 2 mA		 35 mV/V
VRIPPLE Output ripple VIN = 3.6 V, IOUT = 4 mA, COUT = 220 nF 240 mV
IOUT Output current 0 3 mA
PG Power-good threshold
(fraction of nominal output voltage) 		VOFS rising 85%
VOFS falling 62%
RDIS Output discharge resistor Active when rail is disabled 2 kΩ
C Output capacitor Recommended value 110 220 nF
VBIAS REGULATOR
VBIAS Output voltage 16 V
DC output voltage accuracy IOUT = 2 mA –2% 2%
DC load regulation VIN = 3.6 V, IOUT = 0 mA to 4 mA –14 V/A
DC line regulation VINA, VINL, VINR 2.7 V to 6 V,
IOUT = 2 mA		 18 mV/V
VRIPPLE Output ripple VIN = 3.6 V, IOUT = 4 mA, COUT = 220 nF 240 mV
IOUT Output current 0 4 mA
PG Power-good threshold
(fraction of nominal output voltage) 		VOFS rising 85%
VOFS falling 62%
RDIS Output discharge resistor Active when rail is disabled 2 kΩ
C Output capacitor Recommended value 110 220 nF
VRST REGULATOR
VRST Output voltage –10 V
DC output voltage accuracy IOUT = 2 mA –2% 2%
DC load regulation VIN = 3.6 V, IOUT = 0 mA to 4 mA 13 V/A
DC line regulation VINA, VINL, VINR 2.7 V to 6 V,
IOUT = 2 mA		 –21 mV/V
VRIPPLE Output ripple VIN = 3.6 V, IOUT = 4 mA, COUT = 220 nF 240 mV
VREF_VRST Reference voltage 500 mV
IOUT Output current 0 4 mA
PG Power-good threshold –9.1 V
C Output capacitor Recommended value 110 220 nF
VLED BUCK-BOOST
VLED Output voltage range 1.2 5.9 V
Default output voltage SW4/5/6 in OPEN position 3.5
VOVP Output overvoltage protection Clamps buck-boost output 5.9 V
VLED_OVP Fault detection threshold Triggers VLED_OVP interrupt 5.4 V
ISW Switch current limit 1.65 2.2 2.5 A
RDS(ON) MOSFET on resistance Switch A (from VINL to L1) 100 mΩ
Switch B (from L1 to GND) 100
Switch C (from L2 to GND) 100
Switch D (from L2 to VLED) 100
fSW Switching frequency 2.25 MHz
COUT Output capacitance 2 × 10 µF
RGB STROBE CONTROLLER SWITCHES
RDS(ON) Drain-source on resistance SW1, SW2, SW3 50 100 mΩ
SW4, SW5, SW6 40 100
ILEAK Off-state leakage current VDS = 5 V 1 µA
LED CURRENT CONTROL
Vf LED forward voltage ILED = 1 A 4.8 V
ILED Maximum LED drive current VIN = 3.1 V, VLED = 4.4 V 700 mA
VIN = 4 V, VLED = 4.4 V 1000
DC current accuracy, SW4, 5, 6 SWx_IDAC[9:0] = 0x100h
RLIM = 100 mΩ, 0.1%, TA = 25°C		 258 272 286 mA
Transient LED current limit range ILIM[2:0] = 000 260 mA
ILIM[2:0] = 111 1250
trise Current rise time(4) ILED from 5% to 95%, ILED = 300 mA, transient current limit disabled 50 µs
MEASUREMENT SYSTEM (AFE)
G Amplifier gain (PGA) AFE_GAIN[1:0] = 01 1 V/V
AFE_GAIN[1:0] = 10 9.5
AFE_GAIN[1:0] = 11 18
VOFS Input referred offset voltage(4) PGA, AFE_CAL_DIS = 1 –1 1 mV
Comparator –1.5 1.5
tsettle Settling time(4) To 1% of final value 15 µs
To 0.1% of final value 52
fsample Sampling rate(4) 19 kHz
LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL Output low-level IO = 0.5 mA, sink current
(RESETZ, PWR_EN, CMP_OUT)		 0 0.3 V
IO = 5 mA, sink current
(SPI_DOUT, INTZ)		 0 0.3
VOH Output high-level IO = 0.5 mA, source current
(RESETZ, PWR_EN, CMP_OUT)		 1.3 2.5 V
IO = 5 mA, sink current
(SPI_DOUT)		 1.3 2.5
VIL Input low-level TEST, PROJ_ON, LED_SEL0, LED_SEL1, SPI_CSZ, SPI_CLK, SPI_DIN 0.4 V
VIH Input high-level TEST, PROJ_ON, LED_SEL0, LED_SEL1, SPI_CSZ, SPI_CLK, SPI_DIN 1.2 V
I(bias) Input bias current VIO = 3.3 V
Any input pin 		0.5 µA
tdeglitch Deglitch time(4) (PROJ_ON, TEST) pins 1 ms
(LED_SEL0, LED_SEL1) pins 300 ns
INTERNAL OSCILLATOR
fOSC Oscillator frequency 9 MHz
Frequency accuracy TA = –40°C to 85°C –10% 10%
THERMAL SHUTDOWN
TWARN Thermal warning (HOT threshold) 120 °C
Hysteresis 10
TSHTDWN Thermal shutdown (TSD threshold) 150 °C
Hysteresis 15
(1) Full functional but limited parametric performance.
(2) Including rectifying diode.
(3) Contact factory for 100-mA and 300-mA options.
(4) Not tested in production.

6.6 Timing Requirements

VBAT = 3.6 V ±5%, TA = 25°C, CL = 10 pF (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
fCLK Serial clock frequency 0 33.34 MHz
tCLKL Pulse width low, SPI_CLK, 50% level 10 ns
tCLKH Pulse width high, SPI_CLK, 50% level 10 ns
tt Transition time, 20% to 80% level, all signals 0.2 4 ns
tCSCR SPI_CSZ falling to SPI_CLK rising, 50% level 8 ns
tCFCS SPI_CLK falling to SPI_CSZ rising, 50% level 1 ns
tCDS SPI_DIN data setup time, 50% level 7 ns
tCDH SPI_DIN data hold time, 50% level 6 ns
tiS SPI_DOUT data setup time(1), 50% level 10 ns
tiH SPI_DOUT data hold time(1), 50% level 0 ns
tCFDO SPI_CLK falling to SPI_DOUT data valid, 50% level 13 ns
tCSZ SPI_CSZ rising to SPI_DOUT HiZ 6 ns
(1) The DPPxxxx processors send and receive data on the falling edge of the clock.
DLPA1000 spi_timing_lvsb06.gif Figure 1. SPI Timing Diagram

6.7 Typical Characteristics

The maximum output current of the buck-boost is a function of input voltage (VIN), and output voltage (VLED). The relationship between VIN, VLED, and MAX ILED is shown in Figure 2. Please note that VLED is the output of the buck-boost regulator which includes the voltage drop across the sense resistor (100 mΩ), internal strobe control switch (100-mΩ max), and the forward voltage of the LED. For example, to drive 1-A of current through a LED with Vf = 4.2 V, the minimum input voltage needs to be ≥ 3.7 V (VLED = 4.2 V + 1 A × 100 mΩ + 1 A × 100 mΩ = 4.4 V). For an input voltage of 3.1 V and a drive current of 700 mA, the max VLED voltage cannot exceed 4.4 V.
DLPA1000 max_led_out_lvsb06.gif
1. Measured on a typical unit. Note that VLED is the output of the buck-boost regulator and includes the voltage drop across the sense resistor, internal strobe control switch, and the forward voltage of the LED.
Figure 2. Maximum LED Output Current as a Function of Input Voltage (VIN) and BB Output Voltage (VLED)