JAJSFU7E December   2013  – March 2019 DLPC2607

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Typical Current and Power Dissipation
    6. 6.6  I/O Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  Parallel I/F Frame Timing Requirements
    9. 6.9  Parallel I/F General Timing Requirements
    10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
    11. 6.11 BT.656 I/F General Timing Requirements
    12. 6.12 100- to 120-Hz Operational Limitations
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 mDDR Memory Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
    4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Reference Clock
        2. 8.2.2.2 mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Hot-Plug Usage
        2. 8.2.3.2 Maximum Signal Transition Time
        3. 8.2.3.3 Configuration Control
        4. 8.2.3.4 White Point Correction Light Sensor
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 System Power I/O State Considerations
    4. 9.4 Power-Up Initialization Sequence
    5. 9.5 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  Internal ASIC PLL Power
      2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
      3. 10.1.3  SPI Signal Routing
      4. 10.1.4  mDDR Memory and DMD Interface Considerations
      5. 10.1.5  PCB Design
      6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
      7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
      8. 10.1.8  I/F Specific PCB Routing
      9. 10.1.9  Number of Layer Changes
      10. 10.1.10 Stubs
      11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 デバイスの項目表記
        1. 11.1.2.1 デバイス・マーキング
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 付録: パッケージ･オプション
      1. 12.1.1 パッケージ情報

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZVB|176
サーマルパッド・メカニカル・データ

6.6 I/O Characteristics

Voltage and current characteristics for each I/O type signal listed previously in the DLPC2607 table are summarized in I/O Characteristics. All inputs and outputs are LVCMOS.(11)
I/O TYPE DESCRIPTION VCCIO (NOM)
(V)		 VIL(8) (min)
(V)		 VIL (MAX)
(V)		 VIH (MIN)
(V)		 VIH(9) (MAX)
(V)		 IIN(1) (MAX)
(µA)		 VOH(2) (MIN)
(V)		 VOL(3) (MAX)
(V)		 IOH(4) (MIN)
(mA)		 IOL(5) (MIN)
(mA)		 ITS (6) (MAX)
(µA)
I1 Input (STD) 1.8 –0.3 0.5 1.2 3 ±10
I2 Input (FLSH) 1.8 –0.3 0.5 1.2 3 ±10
2.5 –0.3 0.7 1.7 3.6 ±10
3.3 –0.3 0.8 2 3.6 ±10
I3 Input (INTF) 1.8 –0.3 0.5 1.2 3 ±10
2.5 –0.3 0.7 1.7 3.6 ±10
3.3 –0.3 0.8 2 3.6 ±10
I4 Input (REFCLK) 1.8 –0.3 0.5 1.2 3 ±10
O14 1× output (STD/ REFCLK) 1.8 1.25 0.4 2.58 2.89 ±10
O24 1× output (FLSH) 1.8 1.25 0.4 2.58 2.89 ±10
2.5 1.7 0.7 6.2 6.3 ±10
3.3 2.4 0.4 5.29 9.38 ±10
O58 2× output (DMD) 1.8 1.25 0.4 6.41 5.78 ±10
O64(10) 1× output (MEM) 1.8 1.53 0.19 4 4 ±10
O74(10) 1× output (MEM DIFF)(7) 1.8 1.53 0.19 4 4 ±10
B14 1× bidirectional (STD) output 1.8 –0.3 0.5 1.2 3 ±10 1.25 0.4 2.58 2.89 ±10
B18(12) 2× bidirectional (STD) output 1.8 –0.3 0.5 1.2 3 ±10 1.25 0.4 5.15 5.72 ±10
B34 1× bidirectional (INTF) output 1.8 –0.3 0.5 1.2 3 ±10 1.25 0.4 2.58 2.89 ±10
2.5 –0.3 0.7 1.7 3.6 ±10 1.7 0.7 6.2 6.3 ±10
3.3 –0.3 0.8 2 3.6 ±10 2.4 0.4 5.29 9.38 ±10
B38 2× bidirectional (INTF) output 1.8 –0.3 0.5 1.2 3 ±10 2.4 0.4 5.15 5.72 ±10
2.5 –0.3 0.7 1.7 3.6 ±10 1.7 0.7 12.4 12.7 ±10
3.3 –0.3 0.8 2.0 3.6 ±10 1.25 0.4 10.57 18.68 ±10
B64(10) 1× bidirectional (MEM) output 1.8 –0.3 0.57 1.19 2.2 ±10 1.53 0.19 4 4 ±10
(1) Input leakage current with no internal pullup or pulldown. VIN = 0 or VIN = VCCIO where VCCIO = I/O supply voltage
(2) IOH = – rated current
(3) IOL = + rated current
(4) VOH = VOH(max)
(5) VOL = VOL(max)
(6) Tri-state output leakage current. VIN = 0 or VIN = VCCIO where VCCIO = I/O supply voltage
(7) The O74 mDDR differential clock (CK) output is simply a pair of single-ended drivers driven by a true and complementary signal.
(8) VIL(min) is the absolute minimum voltage that can safely be applied to each corresponding pin.
(9) VOH(max) is the maximum voltage that can safely be applied to each corresponding pin.
(10) O64, O74, and B64 buffers are tested to only 100 µA for IOH/IOL due to tester limitations.
(11) Pin PLL_REFCLK_I is a crystal oscillator input pin and is not tested during VIH/VIL testing.
(12) B18 buffers are not tested for IIH.