JAJSFU7E December   2013  – March 2019 DLPC2607

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Typical Current and Power Dissipation
    6. 6.6  I/O Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  Parallel I/F Frame Timing Requirements
    9. 6.9  Parallel I/F General Timing Requirements
    10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
    11. 6.11 BT.656 I/F General Timing Requirements
    12. 6.12 100- to 120-Hz Operational Limitations
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 mDDR Memory Interface Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
    4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Reference Clock
        2. 8.2.2.2 mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Hot-Plug Usage
        2. 8.2.3.2 Maximum Signal Transition Time
        3. 8.2.3.3 Configuration Control
        4. 8.2.3.4 White Point Correction Light Sensor
      4. 8.2.4 Application Curve
  9. Power Supply Recommendations
    1. 9.1 System Power Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 System Power I/O State Considerations
    4. 9.4 Power-Up Initialization Sequence
    5. 9.5 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  Internal ASIC PLL Power
      2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
      3. 10.1.3  SPI Signal Routing
      4. 10.1.4  mDDR Memory and DMD Interface Considerations
      5. 10.1.5  PCB Design
      6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
      7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
      8. 10.1.8  I/F Specific PCB Routing
      9. 10.1.9  Number of Layer Changes
      10. 10.1.10 Stubs
      11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 デバイスの項目表記
        1. 11.1.2.1 デバイス・マーキング
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 付録: パッケージ・オプション
      1. 12.1.1 パッケージ情報

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ZVB|176
サーマルパッド・メカニカル・データ

Pin Configuration and Functions

ZVB Package
176-Pin NFBGA
Bottom View
DLPC2607 dlps030_pin_bot.gif

Pin Functions (1)

PIN I/O CLOCK SYSTEM DESCRIPTION
NAME NO. POWER TYPE
DEVICE INITIALIZATION AND REFERENCE CLOCK(1)
RESETZ J14 VCC18 I1 Async DLPC2607 power-on reset. Self-configuration starts when a low-to-high transition is detected on this pin. All ASIC power and clocks must be stable before this reset is de-asserted (hysteresis buffer). Note that the following seven signals tri-state while RESET is asserted: DMD_PWR_EN, LEDDVR_ON, LED_SEL_0,LED_SEL_1, SPICLK, SPIDOUT, SPICSZ0
Add external pullup or pulldown resistors as needed to these signals to avoid floating inputs.
PLL_REFCLK_I K15 VCC18 (filter) I4 N/A Reference clock crystal input. If an external oscillator is used in place of a crystal, then use this pin as the oscillator Input.
PLL_REFCLK_O J15 O14 N/A Reference clock crystal return. If an external oscillator is used in place of a crystal, then leave this pin unconnected (floating).
FLASH INTERFACE(2)
SPICLK A4 VCC_ FLSH O24 N/A Clock for the external SPI device or devices
SPIDIN B4 I2 SPICLK Serial data input from the external SPI device or devices
SPICSZ0 A5 O24 SPICLK Chip select 0 output for the external SPI flash device. Active low
SPICSZ1 C6 O24 SPICLK Chip select 1 output for the external SPI DLPA1000 device. Active low
SPIDOUT C5 O24 SPICLK Serial data output to the external SPI device or devices. This pin sends address and control information as well as data when programming
MAIN VIDEO DATA AND CONTROL
PARK B8 VCC_ INTF I3 Async DMD park control (active low) is set high to enable typical operation. Establish this setting prior to releasing RESET, or within 500 µs after releasing RESET. It should be set low to a minimum of 500 µs before any power is to be removed from the DLPC2607 (hysteresis buffer).
LED_ENABLE A11 VCC_ INTF I3 Async LED enable (active high input). A logic low on this signal forces LEDDRV_ON low and LED_SEL(1:0) = b00. These signals are enabled 100 ms after LED_ENABLE transitions from low to high (hysteresis buffer).
DBIC_CSZ B10 VCC_ INTF I3 SCL Unused/reserved: Pull up to VCC_INTF.
SCL A10 VCC_ INTF B38 N/A I2C clock (hysteresis buffer) bidirectional, open-drain signal. An external pullup is required. No I2C activity is permitted for a minimum of 100 ms after PARK and RESET are set high.
SDA C10 VCC_ INTF B38 SCL I2C data (hysteresis buffer) bidirectional, open-drain signal. An external pullup is required.
GPIO4_INTF C9 VCC_ INTF B34 Async General purpose I/O 4 (hysteresis buffer). Primary usage is to indicate when auto-initialization is complete (also referred to as INIT-DONE, which is when GPIO4 transitions high then low following release of RESET) and to flag a detected error condition in the form of a logic high, pulsed Interrupt flag subsequent to INIT-DONE.
GPIO5_INTF B9 VCC_ INTF B34 Async General purpose I/O 5 (hysteresis buffer). For applications that use focus motor control with a sensor, this pin is an input that is connected to the motor position sensor. For applications that use non-focus motor control with a sensor, configure this pin with an output at logic 0 and left unconnected.
MAIN VIDEO DATA AND CONTROL PARALLEL RGB MODE BT.656 I/F MODE
PCLK (Hysteresis) D13 VCC_ INTF I3 N/A Pixel clock (7) Pixel clock (7)
PDM_CVS_TE H15 VCC_ INTF B34 ASYNC Parallel data mask (5) Unused (4)
VSYNC_WE H14 VCC_ INTF I3 ASYNC Vsync (6) Unused(4)
HSYNC_CS H13 VCC_ INTF I3 PCLK Hsync (6) Unused (4)
DATEN_CMD G15 VCC_ INTF I3 PCLK Data valid (6) Unused (4)
PDATA[0] G14 VCC_ INTF I3 PCLK Data (3) Data0 (3)
PDATA[1] G13 VCC_ INTF I3 PCLK Data (3) Data1 (3)
PDATA[2] F15 VCC_ INTF I3 PCLK Data (3) Data2 (3)
PDATA[3] F14 VCC_ INTF I3 PCLK Data (3) Data3 (3)
PDATA[4] F13 VCC_ INTF I3 PCLK Data (3) Data4 (3)
PDATA[5] E15 VCC_ INTF I3 PCLK Data (3) Data5 (3)
PDATA[6] E14 VCC_ INTF I3 PCLK Data (3) Data6 (3)
PDATA[7] E13 VCC_ INTF I3 PCLK Data (3) Data7 (3)
PDATA[8] D15 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[9] D14 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[10] C15 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[11] C14 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[12] C13 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[13] B15 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[14] B14 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[15] A15 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[16] A14 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[17] B13 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[18] A13 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[19] C12 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[20] B12 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[21] A12 VCC_ INTF I3 PCLK Data (3) Unused (4)
PDATA[22] C11 VCC_ INTF I3 PCLK Data (3) Unused(4)
PDATA[23] B11 VCC_ INTF I3 PCLK Data (3) Unused (4)
DMD INTERFACE
DMD_D0 M15 VCC18 O58 DMD_DCLK DMD Data Pins. DMD Data pins are double data rate (DDR) signals that are clocked on both edges of DMD_DCLK.
All 15 DMD data signals are use to interface to the WVGA and VGA DMDs; however, only 12 of the 15 are used to interface to an nHD DMD.
The standard nHD interconnect is to utilize pins DMD_D(11:0). However, DMD_D(14:3) must be used to interface to the nHD DMD when the I2C programmable option to reverse the bit-order of the DMD interface pins is selected (DMD Bus Swap Control, I2C: 0xA7).
DMD_D1 N14
DMD_D2 M14
DMD_D3 N15
DMD_D4 P13
DMD_D5 P14
DMD_D6 P15
DMD_D7 R15
DMD_D8 R12
DMD_D9 N11
DMD_D10 P11
DMD_D11 R11
DMD_D12 N10
DMD_D13 P10
DMD_D14 R10
DMD_DCLK N13 N/A DMD Data Clock (DDR)
DMD_LOADB R13 DMD_DCLK DMD Data Load Signal (active low). This signal requires an external pullup to VCC18.
DMD_SCTRL R14 DMD_DCLK DMD Data Serial Control Signal
DMD_TRC P12 DMD_DCLK DMD Data Toggle Rate Control
DMD_DAD_BUS L13 DMD_SAC_CLK DMD DAD Bus Data
DMD_DAD_STRB K13 DMD_SAC_CLK DMD DAD Bus Strobe
DMD_DAD_OEZ M13 Async DMD Reset Driver Output Enable (active low). To properly park the DMD, this signal requires a 30-kΩ to 100-kΩ external pullup resistor connected to VCC18.
DMD_SAC_BUS L15 DMD_SAC_CLK DMD SAC Bus Data
DMD_SAC_CLK L14 N/A DMD SAC Bus Clock
SDRAM INTERFACE
MEM0_CLK_P D1 VCC18 O74 N/A mDDR memory, Differential Memory Clock
MEM0_CLK_N E1 O74
MEM0_A0 P1 O64 MEM_CLK mDDR memory, Multiplexed Row, and Column Address
MEM0_A1 R3
MEM0_A2 R1
MEM0_A3 R2
MEM0_A4 A1
MEM0_A5 B1
MEM0_A6 A2
MEM0_A7 B2
MEM0_A8 D2
MEM0_A9 A3
MEM0_A10 P2
MEM0_A11 B3
MEM0_A12 D3
MEM0_BA0 M3 mDDR memory, Bank Select
MEM0_BA1 P3
MEM0_RASZ P4 mDDR memory, Row Address Strobe (active low)
MEM0_CASZ R4 mDDR memory, Column Address Strobe (active low)
MEM0_WEZ R5 mDDR memory, Write Enable (active low)
MEM0_CSZ J3 mDDR memory, Chip Select (active low)
MEM0_CKE C1 mDDR memory, Clock Enable (active high)
MEM0_LDQS J2 B64 N/A mDDR memory, Lower Byte, R/W Data Strobe
MEM0_LDM J1 O64 MEM0_LDQS mDDR memory, Lower Byte, Write Data Mask
MEM0_DQ0 N1 B64 MEM0_LDQS mDDR memory, Lower Byte, Bidirectional R/W Data
MEM0_DQ1 M2
MEM0_DQ2 M1
MEM0_DQ3 L3
MEM0_DQ4 L2
MEM0_DQ5 K2
MEM0_DQ6 L1
MEM0_DQ7 K1
MEM0_UDQS G1 B64 N/A mDDR memory, Upper Byte, R/W Data Strobe
MEM0_UDM H1 O64 MEM0_UDQS mDDR memory, Upper Byte, Write Data Mask
MEM0_DQ8 H2 B64 MEM0_UDQS mDDR memory, Upper Byte, Bidirectional R/W Data
MEM0_DQ9 G2
MEM0_DQ10 H3
MEM0_DQ11 F3
MEM0_DQ12 F1
MEM0_DQ13 E2
MEM0_DQ14 F2
MEM0_DQ15 E3
LED DRIVER INTERFACE
GPIO1_RPWM N8 VCC18 O14 Async General-purpose I/O 1 (output only). If the DLPA1000 is not used, then this output must be used as the red LED PWM signal used to control the LED current.(8) If the DLPA1000 is used, then this output can be used as a general purpose output controlled by the WPC processor.
GPIO2_GPWM P9 O14 Async General-purpose I/O 2 (output only). If the DLPA1000 is not used, then this output must be used as the green LED PWM signal used to control the LED current.(8) If the DLPA1000 is used, then this output can be used as a general purpose output controlled by the WPC processor.
GPIO3_BPWM R8 O14 Async General-purpose I/O 3 (output only). If the DLPA1000 is not used, then this output must be used as the blue LED PWM signal used to control the LED current.(8) If the DLPA1000 is used, then this output can be used as a general-purpose output controlled by the WPC processor.
LED_SEL_0 R6 O14 Async LED enable SELECT. Controlled by programmable DMD sequence timing (hysteresis buffer).
LED_SEL_1 N6 O14 Async LED_SEL(1:0) Selected LED
00 None
01 Red
10 Green
11 Blue
These outputs should be input directly to the DLPA1000 if used. If the DLPA1000 is not used, then a decode circuit is required to decode the selected LED enable.
LEDDRV_ON P7 O14 Async LED driver enable. Active-high output control to external LED driver logic (master enable). It is driven high 100 ms after LED_ENABLE is driven high and driven low immediately when either LED_ENABLE or PARK is driven low.
DMD_PWR_EN K14 O14 Async DMD power regulator enable (active high). This is an active-high output that should be used to control DMD VOFFSET, VBIAS, and VRESET voltages. DMD_PWR_EN is driven high when the PARK input signal is set high. However, DMD_PWR_EN is held high for 500 µs after the PARK input signal is set low before it is driven low. TI recommends a weak external pulldown resistor to keep this signal at a known state during power-up reset.
WHITE POINT CORRECTION LIGHT SENSOR I/F
CMP_OUT A6 VCC_ 18 I1 Async Successive approximation ADC comparator output (DLPC2607 input). Assumes a successive approximation ADC is implemented with either a light sensor or thermocouple or both feeding one input of an external comparator and the other side of the comparator driven from the CMP_PWM pin of the ASIC. If this function is not used, pull it down to ground (hysteresis buffer).
CMP_PWM B7 O14 Async Successive approximation comparator pulse-width modulation input. Supplies a PWM signal to drive the successive approximation ADC Comparator used in light-to-voltage light sensor applications. If this function is not used, leave it unconnected.
GPIO0_CMPPWR P5 B14 Async Power control signal for the WPC light sensor and other analog support circuits using the DLPC2607 ADC. Alternately, it provides general purpose I/O to the WPC microprocessor internal to the DLPC2607 device. If not used, leave it unconnected (hysteresis buffer).
HWTEST_EN A9 VCC _INTF I3 N/A Manufacturing test enable signal. Connect directly to ground on the PCB for typical operation. Includes weak internal pulldown.
JTAGTDI P6 VCC _18 I1 JTAGTCK JTAG, serial data in. Includes weak internal pullup. (When JTAGRSTZ is held low, this input can be used as ICP/ WPC debug port RXD.)
JTAGTCK N5 N/A JTAG, serial data clock. Includes weak internal pullup.
JTAGTMS N7 JTAGTCK JTAG, test mode select. Includes weak internal pullup.
JTAGTDO R7 O14 JTAGTCK JTAG, serial data out
JTAGRSTZ P8 I1 ASYNC JTAG, RESET (active low). Includes weak internal pullup. This signal must be tied to ground, through an external ≤15-kΩ resistor, for typical operation.
TEST AND DEBUG INTERFACES
TSTPT_0 B6 VCC18 B18 Async Test pin 0 – Sampled as an input test mode selection control upon release of RESET, and then driven as an output. Includes weak internal pulldown.(9)
Normal use: Reserved for test output (ICP/ WPC debug port TXD). Leave open or unconnected for typical use.
Alternative use: If focus motor control is used, use this pin as the motor driver chip enable. Do not apply an external pullup to this pin to avoid putting the DLPC2607 device in a test mode.
TSTPT_1 A8 VCC18 B18 Async Test pin 1 – Sampled as an input test mode selection control upon release of RESET, and then driven as an output. Includes weak internal pulldown.(9)
Normal use: Reserved for test output. Leave open or unconnected for typical use.
Alternative use: If focus motor control is used, use this pin as the motor driver data bit1 (LSB). Do not apply an external pullup to this pin to avoid putting the DLPC2607 device in a test mode.
TSTPT_2 C7 VCC18 B18 Async Test pin 2 – Sampled as an input test mode selection control upon release of RESET, and then driven as an output. Includes weak internal pulldown.(9)
Normal use: Reserved for test output. Leave open or unconnected for typical use.
Alternative use: If focus motor control is used, use this pin as the motor driver data bit2. Do not apply an external pullup to this pin to avoid putting the DLPC2607 device in a test mode.
TSTPT_3 B5 VCC18 B18 Async Test Pin 3 – Sampled as an input test mode selection control upon release of RESET, and then driven as an output. Includes weak internal pulldown.(9)
Normal use: Reserved for test output. Leave open or unconnected for typical use.
Alternative use: If focus motor control is used, use this pin as the motor driver motor driver data bit3. Do not apply an external pullup to this pin to avoid putting the DLPC2607 device in a test mode.
TSTPT_4 A7 VCC18 B18 Async Test pin 4 – Sampled as an input test mode selection control upon release of RESET, and then driven as an output. Includes weak internal pulldown.(9)
Normal use: Reserved for test output. Leave open or unconnected for typical use.
Alternative use: If focus motor control is used, use this pin as the motor driver data bit4 (MSB). Do not apply an external pullup to this pin to avoid putting the DLPC2607 device in a test mode.
Without External Pullup(9) With External Pullup(10)
Enables auto-initialization from flash Disables auto-initialization and facilitates flash programming via I2C of a blank flash
TSTPT_5 C8 VCC18 B18 Async Test pin 5 – Sampled as an input test mode selection control upon release of RESET and then driven as an output. Includes weak internal pulldown.(9)
Normal use: Reserved for test output. Leave open or unconnected for typical use.
Alternative use: Not yet defined. Do not apply an external pullup to this pin to avoid putting the DLPC2607 device in a test mode.
TSTPT_6 N9 VCC18 B18 Async Test pin 6 and PLL REFCLK frequency selection – Sampled as an input test mode selection control upon release of RESET and then driven as an output. Includes a weak internal pulldown.(9)
Normal use: Reserved for test output. Leave open or unconnected for typical use.
Alternative use: Not yet defined.
This pin is sampled upon de-assertion of RESTZ to determine REFCLK frequency selection. DLPC2607 I2C address is set corresponding to the sampled input value as follows:
Without External Pullup(9) With External Pullup(10)
PLL assumes REFCLK = 16.67 MHz PLL assumes REFCLK = 8.33 MHz
TSTPT_7 R9 VCC18 B18 Async Test pin 7 and I2C address selection – Sampled as an input test mode selection control upon release of RESET, and then driven as an output. Includes weak internal pulldown.
Normal use: Reserved for test output. Leave open or unconnected for typical use.
Alternative use: Not yet defined.
This pin is sampled upon deassertion of RESET to determine I2C address selection. DLPC2607 I2C address is set corresponding to the sampled input value as follows:
Without External Pullup(9) With External Pullup(10)
I2C slave Write Address = x36
I2C slave Read Address = x37
I2C slave Write Address = x3A
I2C slave Read Address = x3B
POWER AND GROUND(11)
VDD10 D5, D9, F4, F12, J4, J12, M6, M8, M11 1-V core logic power supply
VDD_PLL H12 1-V power supply for the internal PLL
VCC18 C4, D8, E4, G3, K3, K12, L4, M5, M9, M12, N4, N12 1.8-V power supply for all I/O other than the host, video interface, and SPI flash buses
VCC_FLSH D6 1.8-V, 2.5-V, or 3.3-V power supply for SPI flash bus I/O
VCC_INTF D11, E12 1.8-V, 2.5-V, or 3.3-V power supply for all I/Os on the host or video interface (includes I2C, PDATA, video syncs, PARK, and LED_ENABLE pins)
GND D4, D7, D10, D12, G4, G12, H4, K4, L12, M4, M7, M10 Common ground
RTN_PLL J13 Analog ground return for the PLL (This must be connected to the common ground GND through a ferrite.)
Reserved C2, C3, N2, N3 No connects. Other signals can be routed through the ball on these pins (versus going around them) to ease routing if desired
Each device connected to the serial peripheral interface (SPI) bus must be operated off VCC_FLSH
Each device connected to the SPI bus must be operated off VCC_FLSH
PDATA(23:0) bus mapping is pixel format and source mode dependent.
Pull unused inputs to ground through an external resistor.
Data mask is optional for parallel bus operation. If unused, pull to ground through a resistor.
VSYNC, HSYNC, and data valid polarity is software programmable.
Pixel clock capture edge is software programmable.
The DLPA1000 is not available for initial DLPC2607 design applications. When the DLPA1000 is not used, all LED PWM signals are forced high when LEDDRV_ON = 0, software LED control is disabled, or the sequence stops.
If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor, then this I/O can be left open or unconnected for typical operation. If operation does not call for an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then TI recommends an external pulldown resistor to ensure a logic low.
External pullup resistor must be 15 kΩ or less.
134 total signal I/O pins, 38 total power or ground pins, and 4 total reserved pins