JAJSF42B April   2018  – June 2019 DLPC3478

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      標準的なスタンドアロン・システム
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions - DSI Input Data and Clock
    4.     Pin Functions – DMD Reset and Bias Control
    5.     Pin Functions – DMD Sub-LVDS Interface
    6.     Pin Functions – Peripheral Interface
    7.     Pin Functions – GPIO Peripheral Interface
    8.     Pin Functions – Clock and PLL Support
    9.     Pin Functions – Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  High-Speed Sub-LVDS Electrical Characteristics
    8. 6.8  Low-Speed SDR Electrical Characteristics
    9. 6.9  System Oscillators Timing Requirements
    10. 6.10 Power-Up and Reset Timing Requirements
    11. 6.11 Parallel Interface Frame Timing Requirements
    12. 6.12 Parallel Interface General Timing Requirements
    13. 6.13 BT656 Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Input Source - Frame Rates and 3-D Display Orientation
      2. 7.2.2 Parallel Interface Supports Six Data Transfer Formats
        1. 7.2.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pattern Display
        1. 8.3.1.1 External Pattern Mode
          1. 8.3.1.1.1 8-bit Monochrome Patterns
          2. 8.3.1.1.2 1-Bit Monochrome Patterns
        2. 8.3.1.2 Internal Pattern Mode
          1. 8.3.1.2.1 Free Running Mode
          2. 8.3.1.2.2 Trigger In Mode
      2. 8.3.2 Interface Timing Requirements
        1. 8.3.2.1 Parallel Interface
    4. 8.4 Serial Flash Interface
      1. 8.4.1  Serial Flash Programming
      2. 8.4.2  SPI Signal Routing
      3. 8.4.3  I2C Interface Performance
      4. 8.4.4  Content-Adaptive Illumination Control
      5. 8.4.5  Local Area Brightness Boost
      6. 8.4.6  3-D Glasses Operation
      7. 8.4.7  DMD (Sub-LVDS) Interface
      8. 8.4.8  Calibration and Debug Support
      9. 8.4.9  DMD Interface Considerations
      10. 8.4.10 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DLPC3478 System Design Consideration
    2. 9.2 Typical Application
      1. 9.2.1 3D Depth Scanner with DLP Using External Pattern Streaming Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3D Depth Scanner Using Internal Pattern Streaming Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC3478 Power-Up Initialization Sequence
    3. 10.3 DMD Fast PARK Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2 DLPC3478 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6 Number of Layer Changes
      7. 11.1.7 Stubs
      8. 11.1.8 Terminations
      9. 11.1.9 Routing Vias
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 デバイスの項目表記
        1. 12.1.2.1 デバイスのマーキング
      3. 12.1.3 ビデオ・タイミング・パラメータの定義
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics over Recommended Operating Conditions (4)(5)(6)(7)

PARAMETER TEST CONDITIONS(8)(1) MIN TYP(2) MAX(3) UNIT
V(VDD) + V(VDDLP12) Core current 1.1 V (main 1.1 V) IDLE disabled, 720p, 60 Hz 161 334 mA
IDLE disabled, 720p, 120 Hz 185 368
V(VDD_PLLM) MCG PLL 1.1 V current IDLE disabled, 720p, 60 Hz 4 7 mA
IDLE disabled, 720p, 120 Hz 4 7
V(VDD_PLLD) DCG PLL 1.1 V current IDLE disabled, 720p, 60 Hz 4 7 mA
IDLE disabled, 720p, 120 Hz 4 7
V(VDD) + V(VDD_PLLM) + V(VDD_PLLD) Core Current 1.1 V + MCG PLL 1.1 V current + DCG PLL 1.1 V current IDLE disabled, 720p, 60 Hz 169 348 mA
IDLE disabled, 720p, 120 Hz 193 382
V(VCC18) Main 1.8 V I/O current: 1.8 V power supply for all I/O other than the host or parallel interface and the SPI flash interface. IDLE disabled, 720p, 60 Hz 13 18 mA
This includes sub-LVDS DMD I/O , RESETZ, PARKZ, LED_SEL, CMP, GPIO, IIC1, TSTPT and JTAG pins

SPACE

IDLE disabled, 720p, 120 Hz


SPACE

13 18
V(VCC_INTF) Host or parallel interface I/O current: 1.8 to 3.3 V ( includes IIC0, PDATA, video syncs, and HOST_IRQ pins) IDLE disabled, 720p, 60 Hz 2 3 mA
IDLE disabled, 720p, 120 Hz 4 6
V(VCC_FLSH) Flash interface I/O current: 1.8 to 3.3 V IDLE disabled, 720p, 60 Hz 1 1.5 mA
IDLE disabled, 720p, 120 Hz 1 1.5
V(VCC18) +
V(VCC_INTF) +
V(VCC_FLSH) 		Main 1.8 V I/O current + VCC_INTF current + VCC_FLSH current IDLE disabled, 720p, 60 Hz 16 22.5 mA
IDLE disabled, 720p, 120 Hz 18 25.5
(1) In normal operation while displaying an image with CAIC enabled.
(2) Assumes typical case power PVT condition = nominal process, typical voltage, typical temperature (55°C junction). 720p resolution.
(3) Assumes worse case power PVT condition = corner process, high voltage, high temperature (105°C junction), 720p resolution.
(4) Assumes 12.5% activity factor, 30% clock gating on appropriate domains, and mixed SVT or HVT cells
(5) Programmable host and flash I/O are at minimum voltage (that is 1.8 V) for this typical scenario.
(6) Max currents column use typical motion video as the input. The typical currents column uses SMPTE color bars as the input.
(7) Some applications (that is, high-resolution 3D) may be forced to use 1-oz copper to manage ASIC package heat.
(8) Input image is 1280 × 720 (720p) 24-bits on the parallel interface at the frame rate shown with a 0.3-inch 720p DMD.