184.108.40.206.1 Free Running Mode
In free running mode the DLPC3478 controller generates an internal synchronization signal to display pre-stored patterns. User sends an I2C command to instruct DLPC3478 controller to start download of the 1D patterns from flash memory into DLPC3478 controller’s internal memory and displaying of the 1D patterns.
Figure 22. Free Running Mode
The device displays multiple 1D patterns within an internally-generated VSYNC signal. tExposure (exposure time), tDarkPre and tDarkPost (dark time) are equal for all the 1D patterns within one internally generated VSYNC frame.
Blue LED is configured to be ON for each pattern.
TRIG_OUT_1 (Frame Trigger) is configured active high polarity and will have a minimum pulse width of 20 microseconds. TRIG_OUT_1 delay (tD1) is configured with respect to internally generated VSYNC.
TRIG_OUT_2 (Pattern Trigger) is configured active high polarity and stays active during the pattern exposure. TRIG_OUT_2 delay (tD2) is configured with reference to the start of each pattern.
VSYNC is generated internally according to different sets of patterns stored in the SPI flash memory.