JAJSF42B April 2018 – June 2019 DLPC3478
The parallel interface complies with standard graphics interface protocol, which includes a vertical sync signal (VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit data bus (PDATA), and a pixel clock (PCLK). The polarity of both syncs and the active edge of the clock are programmable. Figure 4 shows the relationship of these signals. The data valid signal (DATAEN_CMD) is optional in that the DLPC3478 provides auto-framing parameters that can be programmed to define the data valid window based on pixel and line counting relative to the horizontal and vertical syncs.
In addition to these standard signals, an optional side-band signal (PDM_CVS_TE) is available, which allows periodic frame updates to be stopped without losing the displayed image. When PDM_CVS_TE is active, it acts as a data mask and does not allow the source image to be propagated to the display. A programmable PDM polarity parameter determines if it is active high or active low. This parameter defaults to make PDM_CVS_TE active high. If this function is not desired, tie PDM_CVS_TE to a logic low signal on the PCB. The device allows PDM_CVS_TE to change only during vertical blanking.
VSYNC_WE must remain active at all times (in lock-to-VSYNC mode) or the display sequencer stops and causes the LEDs to be turned off.