JAJSF42B April   2018  – June 2019 DLPC3478

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      標準的なスタンドアロン・システム
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions - DSI Input Data and Clock
    4.     Pin Functions – DMD Reset and Bias Control
    5.     Pin Functions – DMD Sub-LVDS Interface
    6.     Pin Functions – Peripheral Interface
    7.     Pin Functions – GPIO Peripheral Interface
    8.     Pin Functions – Clock and PLL Support
    9.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  High-Speed Sub-LVDS Electrical Characteristics
    8. 6.8  Low-Speed SDR Electrical Characteristics
    9. 6.9  System Oscillators Timing Requirements
    10. 6.10 Power-Up and Reset Timing Requirements
    11. 6.11 Parallel Interface Frame Timing Requirements
    12. 6.12 Parallel Interface General Timing Requirements
    13. 6.13 BT656 Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Input Source - Frame Rates and 3-D Display Orientation
      2. 7.2.2 Parallel Interface Supports Six Data Transfer Formats
        1. 7.2.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pattern Display
        1. 8.3.1.1 External Pattern Mode
          1. 8.3.1.1.1 8-bit Monochrome Patterns
          2. 8.3.1.1.2 1-Bit Monochrome Patterns
        2. 8.3.1.2 Internal Pattern Mode
          1. 8.3.1.2.1 Free Running Mode
          2. 8.3.1.2.2 Trigger In Mode
      2. 8.3.2 Interface Timing Requirements
        1. 8.3.2.1 Parallel Interface
    4. 8.4 Serial Flash Interface
      1. 8.4.1  Serial Flash Programming
      2. 8.4.2  SPI Signal Routing
      3. 8.4.3  I2C Interface Performance
      4. 8.4.4  Content-Adaptive Illumination Control
      5. 8.4.5  Local Area Brightness Boost
      6. 8.4.6  3-D Glasses Operation
      7. 8.4.7  DMD (Sub-LVDS) Interface
      8. 8.4.8  Calibration and Debug Support
      9. 8.4.9  DMD Interface Considerations
      10. 8.4.10 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DLPC3478 System Design Consideration
    2. 9.2 Typical Application
      1. 9.2.1 3D Depth Scanner with DLP Using External Pattern Streaming Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3D Depth Scanner Using Internal Pattern Streaming Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC3478 Power-Up Initialization Sequence
    3. 10.3 DMD Fast PARK Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2 DLPC3478 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6 Number of Layer Changes
      7. 11.1.7 Stubs
      8. 11.1.8 Terminations
      9. 11.1.9 Routing Vias
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 デバイスの項目表記
        1. 12.1.2.1 デバイスのマーキング
      3. 12.1.3 ビデオ・タイミング・パラメータの定義
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Serial Flash Interface

DLPC3478 device uses an external SPI serial flash memory device for configuration support. The minimum required size is dependent on the desired minimum number of sequences, CMT tables, and splash options while the maximum supported is 16 Mb.

For access to flash, the DLPC3478 device uses a single SPI interface operating at a programmable frequency complying to industry standard SPI flash protocol. The programmable SPI frequency is defined to be equal to 180 MHz/N, where N is a programmable value between 5 to 127 providing a range from 36.0 to 1.41732 MHz. Note that this results in a relatively large frequency step size in the upper range (for example, 36 MHz, 30 MHz, 25.7 MHz, 22.5 MHz, and so forth) and thus this must be taken into account when choosing a flash device.

The device supports two independent SPI chip selects; however, the flash must be connected to SPI chip select zero (SPI0_CSZ0) because the boot routine is only executed from the device connected to chip select zero (SPI0_CSZ0). The boot routine uploads program code from flash to program memory, then transfers control to an auto-initialization routine within program memory. The device asserts the HOST_IRQ output signal high while auto-initialization is in progress, then drives it low to signal its completion to the host processor. Only after auto-initialization is complete is the device ready to receive commands through I2C.

The device supports any flash device that is compatible with the modes of operation, features, and performance as defined in Table 5 and Table 6.

Table 5. SPI Flash Required Features or Modes of Operation

FEATURE DLPC3478 REQUIREMENT
SPI interface width Single
SPI protocol SPI mode 0
Fast READ addressing Auto-incrementing
Programming mode Page mode
Page size 256 B
Sector size 4 KB sector
Block size any
Block protection bits 0 = Disabled
Status register bit(0) Write in progress (WIP) \{also called flash busy\}
Status register bit(1) Write enable latch (WEN)
Status register bits(6:2) A value of 0 disables programming protection
Status register bit(7) Status register write protect (SRWP)
Status register bits(15:8)
(that is expansion status byte)
The device supports only single-byte status register R/W command execution, and thus may not be compatible with flash devices that contain an expansion status byte. However, as long as expansion status byte is considered optional in the byte 3 position and any write protection control in this expansion status byte defaults to unprotected, then the device shares compatibility with the DLPC3478 device.

To support flash devices with program protection defaults of either enabled or disabled, the DLPC3478 device always assumes the device default is enabled and goes through the process of disabling protection as part of the boot-up process. This process consists of:

  • A write enable (WREN) instruction executed to request write enable, followed by
  • A read status register (RDSR) instruction is then executed (repeatedly as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction is executed that writes 0 to all 8-bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC3478 issues:

  • A write enable (WREN) instruction to request write enable, followed by
  • A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, the program or erase instruction is executed
  • Note the flash automatically clears the write enable status after each program and erase instruction

The specific instruction OpCode and timing compatibility requirements are listed in Table 8 and Table 7. Note however that the device does not read the flash electronic signature ID and thus cannot automatically adapt protocol and clock rate based on the ID.

Table 6. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements

SPI FLASH COMMAND FIRST BYTE
(OPCODE)
SECOND BYTE THIRD BYTE FOURTH BYTE FIFTH BYTE SIXTH BYTE
Fast READ (1 Output) 0x0B ADDRS(0) ADDRS(1) ADDRS(2) dummy DATA(0)(1)
Read status 0x05 n/a n/a STATUS(0)
Write status 0x01 STATUS(0)  (2)
Write enable 0x06
Page program 0x02 ADDRS(0) ADDRS(1) ADDRS(2) DATA(0)(1)
Sector erase (4KB) 0x20 ADDRS(0) ADDRS(1) ADDRS(2)
Chip erase 0xC7
Only the first data byte is show, data continues
DLPC3478 device does not support access to a second/ expansion Write Status byte

The specific and timing compatibility requirements for a DLPC3478 device compatible flash are listed in Table 7 and Table 8.

Table 7. SPI Flash Key Timing Parameter Compatibility Requirements(1)(2)

SPI FLASH TIMING PARAMETER SYMBOL ALTERNATE SYMBOL MIN MAX UNIT
Access frequency (all commands) FR ƒC ≤1.42 MHz
Chip select high time (also called chip select deselect time) tSHSL tCSH ≤200 ns
Output hold time tCLQX tHO ≥0 ns
Clock low to output valid time tCLQV tV ≤ 11 ns
Data in set-up time tDVCH tDSU ≤5 ns
Data in hold time tCHDX tDH ≤5 ns
The timing values are related to the specification of the flash device itself, not the DLPC3478 device .
The DLPC3478 device does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins are typically tied to a logic high on the PCB through an external pullup.

The DLPC3478 device supports 1.8-, 2.5-, or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied with the corresponding voltage. Table 8 contains a list of 1.8-, 2.5-, and 3.3-V compatible SPI serial flash devices supported by DLPC3478 device .

Table 8. Compatible SPI Flash Device Options(1)(2)

DVT(3) DENSITY (Mb) VENDOR PART NUMBER PACKAGE SIZE
1.8-V COMPATIBLE DEVICES
Yes 4 Mb Winbond W25Q40BWUXIG 2 × 3 mm USON
Yes 4 Mb Macronix MX25U4033EBAI-12G 1.43 × 1.94 mm WLCSP
Yes 8 Mb Macronix MX25U8033EBAI-12G 1.68 × 1.99 mm WLCSP
2.5- OR 3.3-V COMPATIBLE DEVICES
Yes 16 Mb Winbond W25Q16CLZPIG 5 × 6 mm WSON
Yes 32 Mb Winbond W25Q32FVSSIG 5.2 x 7.9 mm SOIC
The flash supply voltage must match VCC_FLSH on the DLPC3478 device. Special attention needs to be paid when ordering devices to be sure the desired supply voltage is attained as multiple voltage options are often available under the same base part number.
Beware when considering Numonyx (Micron) serial flash devices as they typically do not have the 4KB sector size needed to be DLPC3478 device compatible.
All of these flash devices appear compatible with the DLPC3478 device , but only those marked with yes in the DVT column have been validated on the EVM reference design. Those marked with no can be used at the ODM’s own risk.