JAJSF42B April 2018 – June 2019 DLPC3478
PRODUCTION DATA.
The DLPC3478 ASIC DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz. The device sub-LVDS interface supports a number of DMD display sizes, and as a function of resolution, not all output data lanes are needed as DMD display resolutions decrease in size. With internal software selection, the device also supports a limited number of DMD interface swap configurations that can help board layout by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 10 shows the four options available for the DLP3010 (.3 720p) DMD specifically.
DLPC3478 ASIC 8 LANE DMD ROUTING OPTIONS | DMD PINS | |||
---|---|---|---|---|
OPTION 1
Swap Control = x0 |
OPTION 2
Swap Control = x2 |
|||
HS_WDATA_D_P
HS_WDATA_D_N |
HS_WDATA_E_P
HS_WDATA_E_N |
Input DATA_p_0
Input DATA_n_0 |
||
HS_WDATA_C_P
HS_WDATA_C_N |
HS_WDATA_F_P
HS_WDATA_F_N |
Input DATA_p_1
Input DATA_n_1 |
||
HS_WDATA_B_P
HS_WDATA_B_N |
HS_WDATA_G_P
HS_WDATA_G_N |
Input DATA_p_2
Input DATA_n_2 |
||
HS_WDATA_A_P
HS_WDATA_A_N |
HS_WDATA_H_P
HS_WDATA_H_N |
Input DATA_p_3
Input DATA_n_3 |
||
HS_WDATA_H_P
HS_WDATA_H_N |
HS_WDATA_A_P
HS_WDATA_A_N |
Input DATA_p_4
Input DATA_n_4 |
||
HS_WDATA_G_P
HS_WDATA_G_N |
HS_WDATA_B_P
HS_WDATA_B_N |
Input DATA_p_5
Input DATA_n_5 |
||
HS_WDATA_F_P
HS_WDATA_F_N |
HS_WDATA_C_P
HS_WDATA_C_N |
Input DATA_p_6
Input DATA_n_6 |
||
HS_WDATA_E_P
HS_WDATA_E_N |
HS_WDATA_D_P
HS_WDATA_D_N |
Input DATA_p_7
Input DATA_n_7 |