JAJSF42B April 2018 – June 2019 DLPC3478
The sub-LVDS HS interface waveform quality and timing on the DLPC3478 device ASIC is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.
As an example, DMD interface system timing margin can be calculated as follows:
The data sheets for the DMD devices include I/O timing parameters and DMD I/O timing parameters. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI degradation is a more complicated adjustment.
In an attempt to minimize the signal integrity analysis that would otherwise be required, use these PCB design guidelines as a reference of an interconnect system to satisfy both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Be sure to compare any variation from these recommendations with PCB signal integrity analysis or lab measurements.
|DMD_HS Differential Signals||DMD_LS Signals|