JAJSF42B April   2018  – June 2019 DLPC3478

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      標準的なスタンドアロン・システム
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions - DSI Input Data and Clock
    4.     Pin Functions – DMD Reset and Bias Control
    5.     Pin Functions – DMD Sub-LVDS Interface
    6.     Pin Functions – Peripheral Interface
    7.     Pin Functions – GPIO Peripheral Interface
    8.     Pin Functions – Clock and PLL Support
    9.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  High-Speed Sub-LVDS Electrical Characteristics
    8. 6.8  Low-Speed SDR Electrical Characteristics
    9. 6.9  System Oscillators Timing Requirements
    10. 6.10 Power-Up and Reset Timing Requirements
    11. 6.11 Parallel Interface Frame Timing Requirements
    12. 6.12 Parallel Interface General Timing Requirements
    13. 6.13 BT656 Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Input Source - Frame Rates and 3-D Display Orientation
      2. 7.2.2 Parallel Interface Supports Six Data Transfer Formats
        1. 7.2.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pattern Display
        1. 8.3.1.1 External Pattern Mode
          1. 8.3.1.1.1 8-bit Monochrome Patterns
          2. 8.3.1.1.2 1-Bit Monochrome Patterns
        2. 8.3.1.2 Internal Pattern Mode
          1. 8.3.1.2.1 Free Running Mode
          2. 8.3.1.2.2 Trigger In Mode
      2. 8.3.2 Interface Timing Requirements
        1. 8.3.2.1 Parallel Interface
    4. 8.4 Serial Flash Interface
      1. 8.4.1  Serial Flash Programming
      2. 8.4.2  SPI Signal Routing
      3. 8.4.3  I2C Interface Performance
      4. 8.4.4  Content-Adaptive Illumination Control
      5. 8.4.5  Local Area Brightness Boost
      6. 8.4.6  3-D Glasses Operation
      7. 8.4.7  DMD (Sub-LVDS) Interface
      8. 8.4.8  Calibration and Debug Support
      9. 8.4.9  DMD Interface Considerations
      10. 8.4.10 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DLPC3478 System Design Consideration
    2. 9.2 Typical Application
      1. 9.2.1 3D Depth Scanner with DLP Using External Pattern Streaming Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3D Depth Scanner Using Internal Pattern Streaming Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC3478 Power-Up Initialization Sequence
    3. 10.3 DMD Fast PARK Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2 DLPC3478 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6 Number of Layer Changes
      7. 11.1.7 Stubs
      8. 11.1.8 Terminations
      9. 11.1.9 Routing Vias
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 デバイスの項目表記
        1. 12.1.2.1 デバイスのマーキング
      3. 12.1.3 ビデオ・タイミング・パラメータの定義
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Design Requirements

A high-accuracy, 3D depth scanner product is created by using a DLP chipset comprised of DLP3010 DMD, DLPC3478 controller and DLPA200x or DLPA300x PMIC and LED driver. The DLPC3478 simplifies the pattern generation, the DLPA200x or DLPA300x provides the needed analog functions and DMD displays the required patterns for accurate 3D depth capture.

In addition to the three DLP devices in the chipset, other components may be required to complete the application. Minimally, a flash component is required to store patterns, the software, and the firmware in order to control the DLPC3478 controller.

DLPC3478 controller supports any illumination source including IR light source (LEDs or VCSE), UV light source or visible light source (Red, Green or Blue LEDs or lasers).

For connecting the DLPC3478 controller to the host processing for receiving patterns or video data parallel interface is used. Connect an I2C iinterface to the host processor to send commands to the DLPC3478 controller. The only power supplies needed external to the projector are the battery (SYSPWR) and a regulated 1.8-V supply. A single signal (PROJ_ON) controls the entire DLP system power. When PROJ_ON is high, the DLP system turns on and when PROJ_ON is low, the DLPC3478 turns off and draws only a few microamperes of current on SYSPWR. When PROJ_ON is low, the 1.8-V power supply can remain at 1.8 V for use by other sub systems. When PROJ_ON is low, the DLPA200x or DLPA300x 000 draws no current on the 1.8-V supply.