JAJSF42B April 2018 – June 2019 DLPC3478
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | ||
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NAME | NUMBER | |||
HWTEST_EN | C10 | I6 | Manufacturing test enable signal. Connect this signal directly to ground on the PCB for normal operation. | |
PARKZ | C13 | I6 | DMD fast PARK control (active low Input) (hysteresis buffer). PARKZ must be set high to enable normal operation. Set PARKZ high prior to releasing RESETZ (that is, prior to the low-to-high transition on the RESETZ input). Set PARKZ low for a minimum of 32 µs before any power is removed from the DLPC3478 such that the fast DMD PARK operation can be completed. Note for PARKZ, use fast PARK control only when loss of power is eminent and beyond the control of the host processor (for example, when the external power source has been disconnected or the battery has dropped below a minimum level). The longest lifetime of the DMD may not be achieved with the fast PARK operation. The longest lifetime is achieved with a normal PARK operation. Because of this, PARKZ is typically used in conjunction with a normal PARK request control input through GPIO_08. The difference being that when the host sets PROJ_ON low, which connects to both GPIO_08 and the DLPA200x or DLPA300x PMIC chip, the takes much longer than 32 µs to park the mirrors. The DLPA200x or DLPA300x holds on all power supplies, and keep RESETZ high, until the longer mirror parking has completed. This longer mirror parking time, of up to 20 ms, ensures the longest DMD lifetime and reliability.
The DLPA200x or DLPA300x monitors power to the and detects an eminent power loss condition and drives the PARKZ signal accordingly. |
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Reserved | P12 | I6 | TI internal use. Leave unconnected. | |
Reserved | P13 | I6 | TI internal use. Leave unconnected. | |
Reserved | N13(1) | O1 | TI internal use. Leave unconnected. | |
Reserved | N12(1) | O1 | TI internal use. Leave unconnected. | |
Reserved | M13 | I6 | TI internal use. Leave unconnected. | |
Reserved | N11 | I6 | TI internal use. Leave unconnected. | |
Reserved | P11 | I6 | TI internal use
This pin must be tied to ground, through an external 8-kΩ, or less, resistor for normal operation. Failure to tie this pin low during normal operation causes startup and initialization problems. |
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RESETZ | C11 | I6 | power-on reset (active low input) (hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All ASIC power and clocks must be stable before this reset is de-asserted. Note that the following signals become tri-stated while RESETZ is asserted:
SPI0_CLK, SPI0_DOUT, SPI0_CSZ0, SPI0_CSZ1, and GPIO(19:00) External pullups or downs (as appropriate) are typically added to all tri-stated output signals listed (including bidirectional signals to be configured as outputs) to avoid floating ASIC outputs during reset if connected to devices on the PCB that can malfunction. For SPI, at a minimum, any chip selects connected to the devices typically have a pullup. Unused bidirectional signals can be functionally configured as outputs to avoid floating ASIC inputs after RESETZ is set high. The following signals are forced to a logic low state while RESETZ is asserted and corresponding I/O power is applied: LED_SEL_0, LED_SEL_1 and DMD_DEN_ARSTZ No signals operate in active state while RESETZ is asserted. Note that no I2C activity is permitted for a minimum of 500 ms after RESETZ (and PARKZ) are set high. |
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TSTPT_0 | R12 | B1 | Test pin 0 (includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ, and then driven as an output.
Normal use: reserved for test output. Leave open for normal use. Note: Do not apply an external pullup component to this pin to avoid putting the in a test mode. |
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Without external pullup (2)
Feeds TMSEL(0) |
With external pullup(3)
Feeds TMSEL(0) |
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TSTPT_1 | R13 | B1 | Test pin 1 (includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use. Note: Do not apply an external pullup component to this pin to avoid putting the in a test mode. |
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Without external pullup(2)
Feeds TMSEL(1) |
With external pullup(3)
Feeds TMSEL(1) |
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TSTPT_2 | R14 | B1 | Test pin 2 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use. Note: Do not apply an external pullup component to this pin to avoid putting the in a test mode. |
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Without external pullup(2)
Feeds TMSEL(2) |
With external pullup(3)
Feeds TMSEL(2) |
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TSTPT_3 | R15 | B1 | Test pin 3 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for for test output. Leave open for normal use. |
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TSTPT_4 | P14 | B1 | Test pin 4 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use. Reserved for TRIG_OUT_1 signal (Output). |
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TSTPT_5 | P15 | B1 | Test pin 5 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open or unconnected for normal use. |
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TSTPT_6 | N14 | B1 | Test pin 6 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use. Alternative use: none. External logic shall not unintentionally pull this pin high to avoid putting the in a test mode. |
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TSTPT_7 | N15 | B1 | Test pin 7 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use. |
PIN | I/O | DESCRIPTION | ||
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NAME | NUMBER | PARALLEL RGB MODE | BT656 INTERFACE MODE | |
PCLK | P3 | I11 | Pixel clock(6) | Pixel clock(6) |
PDM_CVS_TE | N4 | B5 | Parallel data mask(3) | Unused(2) |
VSYNC_WE | P1 | I11 | Vsync(5) | Unused(2) |
HSYNC_CS | N5 | I11 | Hsync(5) | Unused(2) |
DATAEN_CMD | P2 | I11 | Data Valid(5) | Unused(2) |
(TYPICAL RGB 888) | ||||
PDATA_0
PDATA_1 PDATA_2 PDATA_3 PDATA_4 PDATA_5 PDATA_6 PDATA_7 |
K2
K1 L2 L1 M2 M1 N2 N1 |
I11 | Blue (bit weight 1)
Blue (bit weight 2) Blue (bit weight 4) Blue (bit weight 8) Blue (bit weight 16) Blue (bit weight 32) Blue (bit weight 64) Blue (bit weight 128) |
BT656_Data (0)
BT656_Data (1) BT656_Data (2) BT656_Data (3) BT656_Data (4) BT656_Data (5) BT656_Data (6) BT656_Data (7) |
(TYPICAL RGB 888) | ||||
PDATA_8
PDATA_9 PDATA_10 PDATA_11 PDATA_12 PDATA_13 PDATA_14 PDATA_15 |
R1
R2 R3 P4 R4 P5 R5 P6 |
I11 | Green (bit weight 1)
Green (bit weight 2) Green (bit weight 4) Green (bit weight 8) Green (bit weight 16) Green (bit weight 32) Green (bit weight 64) Green (bit weight 128) |
Unused |
(TYPICAL RGB 888) | ||||
PDATA_16
PDATA_17 PDATA_18 PDATA_19 PDATA_20 PDATA_21 PDATA_22 PDATA_23 |
R6
P7 R7 P8 R8 P9 R9 P10 |
I11 | Red (bit weight 1)
Red (bit weight 2) Red (bit weight 4) Red (bit weight 8) Red (bit weight 16) Red (bit weight 32) Red (bit weight 64) Red (bit weight 128) |
Unused |
3DR | N6 | 3D reference
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Added PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | MIPI DSI MODE | |
DCLKN
DCLKP |
E2
E1 |
B10 | Not supported in this device. This pin must remain unconnected and left floating. |
DD0N
DD0P DD1N DD1P DD2N DD2P DD3N DD3P |
G2
G1 F2 F1 D2 D1 C2 C1 |
B10 | Not supported in this device. This pin must remain unconnected and left floating. |
RREF | F3 | Not supported in this device. This pin must remain unconnected and left floating. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
DMD_DEN_ARSTZ | B1 | O2 | DMD driver enable (active high)/ DMD reset (active low). Assuming the corresponding I/O power is supplied, this signal is driven low after the DMD is parked and before power is removed from the DMD. If the 1.8-V power to the is independent of the 1.8-V power to the DMD, then TI recommends a weak, external pulldown resistor to hold the signal low in the event power is inactive while DMD power is applied. |
DMD_LS_CLK | A1 | O3 | DMD, low speed interface clock |
DMD_LS_WDATA | A2 | O3 | DMD, low speed serial write data |
DMD_LS_RDATA | B2 | I6 | DMD, low speed serial read data |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
DMD_HS_CLK_P
DMD_HS_CLK_N |
A7
B7 |
O4 | DMD high speed interface |
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N DMD_HS_WDATA_G_P DMD_HS_WDATA_G_N DMD_HS_WDATA_F_P DMD_HS_WDATA_F_N DMD_HS_WDATA_E_P DMD_HS_WDATA_E_N DMD_HS_WDATA_D_P DMD_HS_WDATA_D_N DMD_HS_WDATA_C_P DMD_HS_WDATA_C_N DMD_HS_WDATA_B_P DMD_HS_WDATA_B_N DMD_HS_WDATA_A_P DMD_HS_WDATA_A_N |
A3
B3 A4 B4 A5 B5 A6 B6 A8 B8 A9 B9 A10 B10 A11 B11 |
O4 | DMD high speed interface lanes, write data bits: (The true numbering and application of the DMD_HS_DATA pins are software configuration dependent) |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NUMBER | |||
CMP_OUT | A12 | I6 | Successive approximation ADC comparator output ( Input). Assumes a successive approximation ADC is implemented with a WPC light sensor and/or a thermistor feeding one input of an external comparator and the other side of the comparator is driven from the ASIC’s CMP_PWM pin. Typically pulled-down to ground if this function is not used. (hysteresis buffer) | |
CMP_PWM | A15 | O1 | Successive approximation comparator pulse-duration modulation (output). Supplies a PWM signal to drive the successive approximation ADC comparator used in WPC light-to-voltage sensor applications. Leave unconnected if this function is not used. | |
HOST_IRQ(2) | N8 | O9 | Host interrupt (output)
HOST_IRQ indicates when the auto-initialization is in progress and most importantly when it completes. The tri-states this output during reset and assumes that an external pullup is in place to drive this signal to its inactive state. |
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IIC0_SCL | N10 | B7 | I2C slave (port 0) SCL (bidirectional, open-drain signal with input hysteresis): An external pullup is required. The slave I2C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH specification of the slave I2C input buffers). | |
Reserved | R11 | B8 | TI internal use. TI recommends an external pullup resistor. | |
IIC0_SDA | N9 | B7 | I2C slave (port 0) SDA. (bidirectional, open-drain signal with input hysteresis): An external pullup is required. The slave I2C port is the control port of ASIC. The slave I2C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH specification of the slave I2C input buffers). | |
Reserved | R10 | B8 | TI internal use. TI recommends an external pullup resistor. | |
LED_SEL_0 | B15 | O1 | LED enable select. Controlled by programmable DMD sequence | |
Timing
LED_SEL(1:0) 00 01 10 11 |
Enabled LED
DLPA200x / DLPA300x application None Red Green Blue |
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LED_SEL_1 | B14 | O1 | These signals are driven low when RESETZ is asserted and the corresponding I/O power is supplied and continues throughout the auto-initialization process. A weak, external pulldown resistor is still recommended to ensure that the LEDs are disabled when I/O power is not applied. | |
SPI0_CLK | A13 | O13 | Synchronous serial port 0, clock | |
SPI0_CSZ0 | A14 | O13 | SPI port 1, chip select 0 (active low output)
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during ASIC reset assertion. |
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SPI0_CSZ1 | C12 | O13 | SPI port 1, chip select 1 (active low output)
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during ASIC reset assertion. |
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SPI0_DIN | B12 | I12 | Synchronous serial port 0, receive data in | |
SPI0_DOUT | B13 | O13 | Synchronous serial port 0, transmit data out |
PIN | I/O | DESCRIPTION(2) | |||||
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NAME | NUMBER | ||||||
GPIO_19 | M15 | B1 | General purpose I/O 19 (hysteresis buffer). Options:
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GPIO_18 | M14 | B1 | General purpose I/O 18 (hysteresis buffer). Options:
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GPIO_17 | L15 | B1 | General purpose I/O 17 (hysteresis buffer). Options:
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GPIO_16 | L14 | B1 | General purpose I/O 16 (hysteresis buffer). Options:
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GPIO_15 | K15 | B1 | General purpose I/O 15 (hysteresis buffer). Options:
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GPIO_14 | K14 | B1 | General purpose I/O 14 (hysteresis buffer). Options:
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GPIO_13 | J15 | B1 | General purpose I/O 13 (hysteresis buffer). Options:
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GPIO_12 | J14 | B1 | General purpose I/O 12 (hysteresis buffer). Options:
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GPIO_11 | H15 | B1 | General purpose I/O 11 (hysteresis buffer). Options:
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GPIO_10 | H14 | B1 | General Purpose I/O 10 (hysteresis buffer). Options:
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GPIO_09 | G15 | B1 | General purpose I/O 09 (hysteresis buffer). Options:
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GPIO_08 | G14 | B1 | General purpose I/O 08 (hysteresis buffer). Options:
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GPIO_07 | F15 | B1 | General purpose I/O 07 (hysteresis buffer). Options:
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GPIO_06 | F14 | B1 | General purpose I/O 06 (hysteresis buffer). Option:
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GPIO_05 | E15 | B1 | General purpose I/O 05 (hysteresis buffer). Options:
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GPIO_04 | E14 | B1 | General purpose I/O 04 (hysteresis buffer). Options:
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GPIO_03 | D15 | B1 | General purpose I/O 03 (hysteresis buffer). Options:
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GPIO_02 | D14 | B1 | General purpose I/O 02 (hysteresis buffer). Options:
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GPIO_01 | C15 | B1 | General purpose I/O 01 (hysteresis buffer). Options:
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GPIO_00 | C14 | B1 | General purpose I/O 00 (hysteresis buffer). Options:
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PIN | I/O | DESCRIPTION | |
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NAME | NUMBER | ||
PLL_REFCLK_I | H1 | I11 | Reference clock crystal input. If the application uses an external oscillator instead of a crystal, use this pin as the oscillator input. |
PLL_REFCLK_O | J1 | O5 | Reference clock crystal return. If the application uses an external oscillator instead of a crystal, leave this pin unconnected (floating with no added capacitive load). |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
VDD | C5, D5, D7, D12, J4, J12, K3, L4, L12, M6, M9, D9, D13, F13, H13, L13, M10, D3, E3 | PWR | Core power 1.1 V (main 1.1 V) |
VDDLP12 | C3 | PWR | Reserved |
VSS | Common to all package types
C4, D6, D8, D10, E4, E13, F4, G4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12, G13, C6, C8 Only available on F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9, K10 |
GND | Core ground (eDRAM, I/O ground, thermal ground) |
VCC18 | C7, C9, D4, E12, F12, K13, M11 | PWR | All 1.8-V I/O power:
(1.8-V power supply for all I/O other than the host or parallel interface and the SPI flash interface. This includes RESETZ, PARKZ LED_SEL, CMP, GPIO, IIC1, TSTPT, and JTAG pins) |
VCC_INTF | M3, M7, N3, N7 | PWR | Host or parallel interface I/O power: 1.8 to 3.3 V (Includes IIC0, PDATA, video syncs, and HOST_IRQ pins) |
VCC_FLSH | D11 | PWR | Flash interface I/O power:1.8 to 3.3 V
(Dedicated SPI0 power pin) |
VDD_PLLM | H2 | PWR | MCG PLL 1.1-V power |
VSS_PLLM | G3 | RTN | MCG PLL return |
VDD_PLLD | J2 | PWR | DCG PLL 1.1-V power |
VSS_PLLD | H3 | RTN | DCG PLL return |
I/O | SUPPLY REFERENCE | ESD STRUCTURE | |
---|---|---|---|
SUBSCRIPT | DESCRIPTION | ||
1 | 1.8 LVCMOS I/O buffer with 8-mA drive | Vcc18 | ESD diode to GND and supply rail |
2 | 1.8 LVCMOS I/O buffer with 4-mA drive | Vcc18 | ESD diode to GND and supply rail |
3 | 1.8 LVCMOS I/O buffer with 24-mA drive | Vcc18 | ESD diode to GND and supply rail |
4 | 1.8 sub-LVDS output with 4-mA drive | Vcc18 | ESD diode to GND and supply rail |
5 | 1.8, 2.5, 3.3 LVCMOS with 4-mA drive | Vcc_INTF | ESD diode to GND and supply rail |
6 | 1.8 LVCMOS input | Vcc18 | ESD diode to GND and supply rail |
7 | 1.8-, 2.5-, 3.3-V I2C with 3-mA drive | Vcc_INTF | ESD diode to GND and supply rail |
8 | 1.8-V I2C with 3-mA drive | Vcc18 | ESD diode to GND and supply rail |
9 | 1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive | Vcc_INTF | ESD diode to GND and supply rail |
11 | 1.8, 2.5, 3.3 LVCMOS input | Vcc_INTF | ESD diode to GND and supply rail |
12 | 1.8-, 2.5-, 3.3-V LVCMOS input | Vcc_FLSH | ESD diode to GND and supply rail |
13 | 1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive | Vcc_FLSH | ESD diode to GND and supply rail |