JAJSF42B April 2018 – June 2019 DLPC3478
Although the DLPC3478 requires an array of power supply voltages, (for example, VDD, VDDLP12, VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), if VDDLP12 is tied to the 1.1-V VDD supply (which is assumed to be the typical configuration), then there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC3478. (This is true for both power-up and power-down scenarios). Similarly, there is no minimum time between powering-up or powering-down the different supplies if VDDLP12 is tied to the 1.1-V VDD supply.
If however VDDLP12 is not tied to the VDD supply, then VDDLP12 must be powered-on after the VDD supply is powered-on, and powered-off before the VDD supply is powered-off. In addition, if VDDLP12 is not tied to VDD, then VDDLP12 and VDD supplies are typically powered on or powered off within 100 ms of each other.
Although there is no risk of damaging the DLPC3478 if the above power sequencing rules are followed, the following additional power sequencing recommendations must be considered to ensure proper system operation.
Note that when VDD core power is applied, but I/O power is not applied, additional leakage current may be drawn. This added leakage does not affect normal DLPC3478 operation or reliability.