JAJSF42B April 2018 – June 2019 DLPC3478
An external power monitor holds the DLPC3478 device in a system reset state during power-up by driving RESETZ to a logic low state. It continues to assert system reset until all ASIC voltages have reached minimum specified voltage levels, PARKZ is asserted high, and input clocks are stable. During this time, the device drives most ASIC outputs to an inactive state and configures all bidirectional signals as inputs to avoid contention. ASIC outputs that are not driven to an inactive state are tri-stated. These include LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0 (see RESETZ pin description for full signal descriptions in Pin Configuration and Functions. After power is stable and the PLL_REFCLK_I clock input to the DLPC3478 is stable, then RESETZ is typically deactivated (set to a logic high). The DLPC3478 then performs a power-up initialization routine that first locks its PLL followed by loading self configuration data from the external flash. Upon release of RESETZ all DLPC3478 I/Os become active. Immediately following the release of RESETZ, the device drives the HOST_IRQ signal high to indicate that the auto initialization routine is in progress. However, because a pullup resistor connects the signal HOST_IRQ, this signal goes high before the DLPC3478 device actively drives it high. Upon completion of the auto-initialization routine, the DLPC3478 drives HOST_IRQ low to indicate the initialization done state of the DLPC3478 device has been reached.
The host processor can start sending I2C commands after HOST_IRQ goes low.