JAJSF42B
April 2018 – June 2019
DLPC3478
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
標準的なスタンドアロン・システム
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions – Board Level Test, Debug, and Initialization
Pin Functions – Parallel Port Input Data and Control
Pin Functions - DSI Input Data and Clock
Pin Functions – DMD Reset and Bias Control
Pin Functions – DMD Sub-LVDS Interface
Pin Functions – Peripheral Interface
Pin Functions – GPIO Peripheral Interface
Pin Functions – Clock and PLL Support
Pin Functions – Power and Ground
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics over Recommended Operating Conditions
6.6
Electrical Characteristics
6.7
High-Speed Sub-LVDS Electrical Characteristics
6.8
Low-Speed SDR Electrical Characteristics
6.9
System Oscillators Timing Requirements
6.10
Power-Up and Reset Timing Requirements
6.11
Parallel Interface Frame Timing Requirements
6.12
Parallel Interface General Timing Requirements
6.13
BT656 Interface General Timing Requirements
6.14
Flash Interface Timing Requirements
7
Parameter Measurement Information
7.1
HOST_IRQ Usage Model
7.2
Input Source
7.2.1
Input Source - Frame Rates and 3-D Display Orientation
7.2.2
Parallel Interface Supports Six Data Transfer Formats
7.2.2.1
PDATA Bus – Parallel Interface Bit Mapping Modes
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Pattern Display
8.3.1.1
External Pattern Mode
8.3.1.1.1
8-bit Monochrome Patterns
8.3.1.1.2
1-Bit Monochrome Patterns
8.3.1.2
Internal Pattern Mode
8.3.1.2.1
Free Running Mode
8.3.1.2.2
Trigger In Mode
8.3.2
Interface Timing Requirements
8.3.2.1
Parallel Interface
8.4
Serial Flash Interface
8.4.1
Serial Flash Programming
8.4.2
SPI Signal Routing
8.4.3
I2C Interface Performance
8.4.4
Content-Adaptive Illumination Control
8.4.5
Local Area Brightness Boost
8.4.6
3-D Glasses Operation
8.4.7
DMD (Sub-LVDS) Interface
8.4.8
Calibration and Debug Support
8.4.9
DMD Interface Considerations
8.4.10
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
DLPC3478 System Design Consideration
9.2
Typical Application
9.2.1
3D Depth Scanner with DLP Using External Pattern Streaming Mode
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curve
9.2.2
3D Depth Scanner Using Internal Pattern Streaming Mode
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curve
10
Power Supply Recommendations
10.1
System Power-Up and Power-Down Sequence
10.2
DLPC3478 Power-Up Initialization Sequence
10.3
DMD Fast PARK Control (PARKZ)
10.4
Hot Plug Usage
10.5
Maximum Signal Transition Time
11
Layout
11.1
Layout Guidelines
11.1.1
PCB Layout Guidelines for Internal ASIC PLL Power
11.1.2
DLPC3478 Reference Clock
11.1.2.1
Recommended Crystal Oscillator Configuration
11.1.3
General PCB Recommendations
11.1.4
General Handling Guidelines for Unused CMOS-Type Pins
11.1.5
Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
11.1.6
Number of Layer Changes
11.1.7
Stubs
11.1.8
Terminations
11.1.9
Routing Vias
11.2
Layout Example
11.3
Thermal Considerations
12
デバイスおよびドキュメントのサポート
12.1
デバイス・サポート
12.1.1
デベロッパー・ネットワークの製品に関する免責事項
12.1.2
デバイスの項目表記
12.1.2.1
デバイスのマーキング
12.1.3
ビデオ・タイミング・パラメータの定義
12.2
関連リンク
12.3
コミュニティ・リソース
12.4
商標
12.5
静電気放電に関する注意事項
12.6
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
ZEZ|201
MPBGAK7
サーマルパッド・メカニカル・データ
発注情報
jajsf42b_oa
6
Specifications