JAJSF42B April 2018 – June 2019 DLPC3478
The following guidelines are recommended to achieve desired ASIC performance relative to the internal PLL. The DLPC3478 contains 2 internal PLLs which have dedicated analog supplies (VDD_PLLM , VSS_PLLM, VDD_PLLD, VSS_PLLD). As a minimum, isolate VDD_PLLx power and VSS_PLLx ground pins using a simple passive filter consisting of two series Ferrites and two shunt capacitors (to widen the spectrum of noise absorption). The recommended values are for one 0.1-µf capacitor and one 0.01-µf capacitor. Place all four components as close to the ASIC as possible. It is critical to keep the leads of the high frequency capacitors as short as possible. Connect both capacitors across VDD_PLLM and VSS_PLLM / VDD_PLLD and VSS_PLLD respectfully on the ASIC side of the Ferrites.
Ferrite bead specification recommendations:
The PCB layout is critical to PLL performance. It is vital to treat the quiet ground and power as analog signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC3478 to both capacitors and then through the series ferrites to the power source. Make the power and ground traces as short as possible, parallel to each other, and as close as possible to each other.