JAJSEP0F April   2013  – May 2019 DLPC350

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. Table 1. Power and Ground Pin Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  I/O Electrical Characteristics
    6. 7.6  I2C0 and I2C1 Interface Timing Requirements
    7. 7.7  Port 1 Input Pixel Interface Timing Requirements
    8. 7.8  Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements
    9. 7.9  System Oscillator Timing Requirements
    10. 7.10 Reset Timing Requirements
    11. 7.11 Video Timing Input Blanking Specification
      1. 7.11.1 Source Input Blanking
    12. 7.12 Programmable Output Clocks Switching Characteristics
    13. 7.13 DMD Interface Switching Characteristics
    14. 7.14 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Power Consumption
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Board Level Test Support
    4. 9.4 Device Functional Modes
      1. 9.4.1 Structured Light Applications
      2. 9.4.2 (LVDS) Receiver Supported Pixel Mapping Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Chipset Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 DLPC350 System Interfaces
            1. 10.2.1.2.1.1 Control Interface
            2. 10.2.1.2.1.2 Input Data Interface
          2. 10.2.1.2.2 DLPC350 System Output Interfaces
            1. 10.2.1.2.2.1 Illumination Interface
            2. 10.2.1.2.2.2 Trigger Interface (Sync Outputs)
          3. 10.2.1.2.3 DLPC350 System Support Interfaces
            1. 10.2.1.2.3.1 Reference Clock
            2. 10.2.1.2.3.2 PLL
            3. 10.2.1.2.3.3 Program Memory Flash Interface
          4. 10.2.1.2.4 DMD Interfaces
            1. 10.2.1.2.4.1 DLPC350 to DMD Digital Data
            2. 10.2.1.2.4.2 DLPC350 to DMD Control Interface
            3. 10.2.1.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  11. 11Power Supply Recommendations
    1. 11.1 System Power and Reset
      1. 11.1.1 Default Conditions
        1. 11.1.1.1 1.2-V System Power
        2. 11.1.1.2 1.8-V System Power
        3. 11.1.1.3 1.9-V System Power
        4. 11.1.1.4 3.3-V System Power
        5. 11.1.1.5 FPD-Link Input LVDS System Power
      2. 11.1.2 System Power-up and Power-down Sequence
      3. 11.1.3 Power-On Sense (POSENSE) Support
      4. 11.1.4 Power-Good (PWRGOOD) Support
      5. 11.1.5 5-V Tolerant Support
      6. 11.1.6 Power Reset Operation
      7. 11.1.7 System Reset Operation
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 DMD Interface Design Considerations
      2. 12.1.2 DMD Termination Requirements
      3. 12.1.3 Decoupling Capacitors
      4. 12.1.4 Power Plane Recommendations
      5. 12.1.5 Signal Layer Recommendations
      6. 12.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 12.1.7 PCB Manufacturing
        1. 12.1.7.1 General Guidelines
        2. 12.1.7.2 Trace Widths and Minimum Spacings
        3. 12.1.7.3 Routing Constraints
        4. 12.1.7.4 Fiducials
        5. 12.1.7.5 Flex Considerations
        6. 12.1.7.6 DLPC350 Thermal Considerations
    2. 12.2 Layout Example
      1. 12.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 12.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 12.2.3 Recommended DLPC350 PLL Layout Configuration
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 ビデオ・タイミング・パラメータの定義
      2. 13.1.2 デバイスの項目表記
      3. 13.1.3 デバイス・マーキング
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 商標
    4. 13.4 Glossary
  14. 14メカニカル、パッケージ、および注文情報
    1. 14.1 Package Option Addendum
      1. 14.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

12.1.7.3 Routing Constraints

In order to meet the specifications listed in the following tables, typically the PCB designer must route these signals manually (not using automated PCB routing software). In case of length matching requirements, routing traces in a serpentine fashion may be required. Keep the number of turns to a minimum and the turn angles no sharper than 45°. Traces must be 0.1 inches from board edges when possible; otherwise they must be 0.05 inches minimum from the board edges. Avoid routing long traces all around the PCB. PCB layout assumes adjacent trace spacing is twice the trace width. However, three times the trace width will reduce crosstalk and significantly help performance.

The maximum and minimum signal routing trace lengths include escape routing.

Table 20. Signal Length Routing Constraints for DMD Interface

SIGNALS MINIMUM SIGNAL ROUTING LENGTH(1) MAXIMUM SIGNAL ROUTING LENGTH(2)
DMD_D(23:0), DMD_DCLK, DMD_TRC, DMD_SCTRL, DMD_LOADB, 2480 mil
(63 mm)		 2953 mil
(75 mm)
DMD_OE, DMD_DRC_STRB, DMD_DRC_BUS, DMD_SAC_CLK, and DMD_SAC_BUS 512 mil
(13 mm)		 5906 mil
(150 mm)
(1) Signal lengths below the stated minimum will likely result in overshoot or undershoot.
(2) DMD-DDR maximum signal length is a function of the DMD_DCLK rate.

Each high-speed, single-ended signal should be routed in relation to its reference signal, such that a constant impedance is maintained throughout the routed trace. Avoid sharp turns and layer switching while keeping total trace lengths to a minimum. The following signals should follow the signal matching requirements described in Table 21.

Table 21. High-Speed Signal Matching Requirements for DMD Interface

SIGNALS REFERENCE SIGNAL MAX MISMATCH UNIT
DMD_D(23:0), DMD_TRC, DMD_SCTRL, DMD_LOADB DMD_DCLK ±200
(±5.08)		 mil
(mm)
DMD_DRC_STRB, DMD_DRC_BUS, DMD_SAC_BUS, DMD_OE DMD_SAC_CLK ±200
(±5.08)		 mil
(mm)

The values in Table 21 apply to the PCB routing only. They do not include any internal package routing mismatch associated with the DLPC350 or DMD. Additional margin can be attained if internal DLPC350 package skew is taken into account. Additionally, to minimize EMI radiation, serpentine routes added to facilitate trace length matching should only be implemented on signal layers between reference planes.

Both the DLPC350 output timing parameters and the DMD input timing parameters include a timing budget to account for their respective internal package routing skew. Thus, additional system margin can be attained by comprehending the package variations and compensating for them in the PCB layout. To increase the system timing margin, TI recommends that the DLPC350 package variation be compensated for (by signal group), but it may not be desirable to compensate for DMD package skew. This is due to the fact that each DMD has a different skew profile, making the PCB layout DMD specific. To use a common PCB design for different DMDs, TI recommends that either the DMD package skew variation not be compensated for on the PCB, or the package lengths for all applicable DMDs being considered. Table 22 provides the DLPC350 package output delay at the package ball for each DMD interface signal.

The total length of all the traces in Table 22 should be matched to the DMD_DCLK trace length. Total trace length includes package skews, PCB length, and DMD flex cable length.

Table 22. DLPC350 Package Skew and Routing Trace Length for the DMD Interface

SIGNAL TOTAL DELAY (Package Skews) PACKAGE PIN
(ps) (mil)
DMD_D0 25.9 152.35 A8
DMD_D1 19.6 115.29 B8
DMD_D2 13.4 78.82 C8
DMD_D3 7.4 43.53 D8
DMD_D4 18.1 106.47 B11
DMD_D5 11.1 65.29 C11
DMD_D6 4.4 25.88 D11
DMD_D7 0.0 0.00 E11
DMD_D8 14.8 87.06 C7
DMD_D9 18.4 108.24 B10
DMD_D10 6.4 37.65 E7
DMD_D11 4.8 28.24 D10
DMD_D12 29.8 175.29 A6
DMD_D13 25.7 151.18 A12
DMD_D14 19.0 111.76 B12
DMD_D15 11.7 68.82 C12
DMD_D16 4.7 27.65 D12
DMD_D17 21.5 126.47 B7
DMD_D18 24.8 145.88 A10
DMD_D19 8.3 48.82 D7
DMD_D20 23.9 140.59 B6
DMD_D21 1.6 9.41 E9
DMD_D22 10.7 62.94 C10
DMD_D23 16.7 98.24 C6
DMD_DCLK 24.8 145.88 A9
DMD_LOADB 18.0 105.88 B9
DMD_SCTRL 11.4 67.06 C9
DMD_TRC 4.6 27.06 D9

Table 23. Routing Priority

SIGNAL ROUTING PRIORITY ROUTING LAYER MATCHING REFERENCE SIGNAL TOLERANCE
DMD_DCLK(1)(2)(3) 1 3 – –
DMD_D[23:0], DMD_SCTRL, DMD_TRC, DMD_LOADB(1)(2)(3)(4) 1 3, 4 DMD_DCLK ±150 mils
P1_A[9:0], P1_B[9:0], P1_C[9:0], P1_HSYNC, P1_VSYNC, P1_DATAEN, P1X_CLK 1 3, 4 P1X_CLK ±0.1 inches
R[A-E]_IN_P, R[A-E]_IN_N, RCK_IN_P, RCK_IN_N 2 3, 4 RCK ±150 mils
Differential signals need to be matched within ±12 mils
(1) Total signal length from the DLPC350 and the DMD, including flex cable traces and PCB signal trace lengths must be held to the lengths specified in Table 20.
(2) Switching routing layers is not permitted except at the beginning and end of a trace.
(3) Minimize vias on DMD traces.
(4) Matching includes PCB trace length plus the DLPC350 package length plus the DMD flex cable length.