SNLS579A April 2018 – November 2018 DP83TC811S-Q1
100BASE-T1 Master and 100BASE-T1 Slave are configured using either hardware bootstraps or through register access.
LED_0 controls the 100BASE-T1 Master and 100BASE-T1 Slave bootstrap configuration. By default, 100BASE-T1 Slave mode is configured because there is an internal pulldown resistor on LED_0 pin. If 100BASE-T1 Master mode configuration through hardware bootstrap is preferred, an external pullup resistor is required.
Additionally, bit in the PMA_CTRL2 Register 0x0834 – MMD1 PMA Control Register #2 controls the 100BASE-T1 Master and 100BASE-T1 Slave configuration. When this bit is set, 100BASE-T1 Master mode is enabled.