SNLS579A April 2018 – November 2018 DP83TC811S-Q1
|BIST Error Count|
|BIST IPG Length|
|15:8||BIST Error Count||RO||0||BIST Error Count:
Holds number of errored bytes received by the PRBS checker. Value in this register is locked and cleared when write is done to Bit. When BIST Error Counter Mode is set to '0', count stops on 0xFF (see register 0x16)
Note: Writing '1' to Bit will lock the counter's value for successive read operation and clear the BIST Error Counter.
|7:0||BIST IPG Length||RW||0111 1101||BIST IPG Length:
Inter Packet Gap (IPG) Length defines the size of the gap (in 4 byte increments) between any 2 successive packets generated by the BIST.
Default value is 0x7D:
0x7D to decimal conversion = 125
125 * 4 bytes = 500 bytes (default)