SNLS579A April 2018 – November 2018 DP83TC811S-Q1
The DP83TC811S-Q1 incorporates an internal PRBS Built-in Self-Test (BIST) circuit to accommodate in-circuit testing and diagnostics. The BIST circuit can be used to test the integrity of transmit and receive data paths. BIST can be enabled while using internal loopbacks (MII, PCS or analog) or external loopback when using a Link Partner configured for Reverse Loopback. BIST simulates pseudo-random data transfer scenarios in format of real packets and Inter-Packet Gap (IPG) on the lines. It allows full control over packet lengths and IPG.
BIST Packet Length is controlled using bits[10:0] in the BICTSR2 Register 0x001C – BIST Control and Status Register #2. BIST IPG Length is controlled using bits[7:0] in the BICTSR1 Register 0x001B – BIST Control and Status Register #1.
BIST is implemented with independent transmit and receive paths, with the transmit clock generating a continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for BIST. Received data is compared to the generated pseudo-random data to determine pass or fail status. The number of error bytes that the PRBS checker received is stored in bits[15:8] of the BICSR1 register. PRBS lock status and sync can be read from the BISTCR Register 0x0016 – BIST Control Register.
PRBS test can be put in continuous mode using bit in the BISCR register. In continuous mode, when the BIST error counter reaches its maximum value, the counter starts counting from zero again. To read the BIST error count, bit in the BICSR1 register must be set to 0b1. This will lock the current number of BIST errors for read-back. Note that setting bit also clears the BIST error counter.