SNLS579A April 2018 – November 2018 DP83TC811S-Q1
PCS Loopback will loop back data prior to it exiting the PCS and entering the PMA. Data received from the MAC on the transmit path is brought through the digital block within the PHY where it is then routed back to the MAC through the receive path. The DP83TC811S-Q1 receive PMA circuitry is configured for isolation to prevent contention.
PCS Loopback is enabled by setting bits[6:2] = 0b0001 in the BISTCR Register 0x0016 – BIST Control Register.