SNLS579A April 2018 – November 2018 DP83TC811S-Q1
The DP83TC811S-Q1 can be set to respond to any of 16 possible PHY addresses through bootstrap pins. The PHY address is latched into the device upon power-up or hardware reset. Each DP83TC811S-Q1 or port sharing PHY on the serial management bus in the system must have a unique PHY address. The DP83TC811S-Q1 supports PHY address strapping values 0 (<0b00000>) through 15 (<0b01111>).
By default, the DP83TC811S-Q1 will latch to a PHY address of 0 (<0b00000>). This address can be changed by adding pullup resistors to bootstrap pins found in Table 19.