SNLS579A April 2018 – November 2018 DP83TC811S-Q1
Reset is activated upon power-up, when RESET is pulled LOW (for the minimum reset pulse time) or if hardware reset is initiated by setting bit in the PHYRCR Register 0x001F – PHY Reset Control Register. All digital circuitry is cleared along with register settings during reset. Once reset completes, device bootstraps are re-sampled and associated bootstrap registers are set accordingly. PMA termination is not present in reset.