SNLS579A April 2018 – November 2018 DP83TC811S-Q1
The Serial Gigabit Media Independent Interface (SGMII) provides a means for data transfer between MAC and PHY with significantly less signal pins (4 pins or 6 pins) compared to MII (14 pins), RMII (7 pins) or RGMII (12 pins). SGMII uses low-voltage differential signaling (LVDS) to reduce emissions and improve signal quality.
The DP83TC811S-Q1 SGMII is capable of operating in either 4-wire or 6-wire mode. Only 4-wire SGMII is configurable through hardware bootstraps. To enable 6-wire SGMII, bit in the SGMII_CTRL1 Register 0x0432 – SGMII Control Register #1 must be set. In 4-wire operation, two differential pairs are used to transmit and receive data. Clock and data recovery are performed in the MAC and in the PHY. If the MAC is not capable of recovering the clock from the receive data stream, 6-wire operation can be enabled to output a differential clock that is synchronous with receive data.
Because the DP83TC811S-Q1 operates at 100-Mbps, the 1.25-Gbps rate of the SGMII is excessive. The SGMII specification allows for 100-Mbps operation by replicating each byte within a frame 10 times. Frame elongation takes place above the IEEE 802.3 PCS layer, which prevents the start-of-frame delimiter from appearing more than once.
Because the DP83TC811S-Q1 only supports 100-Mbps speed, SGMII Auto-Negotitation can be disabled by setting bit = 0b0 in the .
The SGMII signals are summarized in Table 16.
|Data Signals||TX_M, TX_P|
|Clock Signal (6-Wire)||RXCLK_M, RXCLK_P|