SNLS579A April 2018 – November 2018 DP83TC811S-Q1
IEEE 802.3bw uses 4B3B encoding (3B4B decoding), reducing a 4-bit data path operating at 25 MHz down to a 3-bit data path operating at 33.334 MHz. For frames and inter-packet gaps that are not divisible by three, one to two stuff bits are added at the end of a transmitted frame. These stuff bits are removed by the link partner before the data is routed to the MAC, making it completely transparent to layers above the Physical layer. These stuff bits cause frame jitter.
The DP83TC811S-Q1 supports an IEEE 1588 indication pulse at the SFD (start of frame delimiter) for receive and transmit paths. The 1588 SFD pulse indicates the actual time the symbol is presented on the lines (for transmit), or the first symbol received (for receive), which provides a deterministic reference point. The pulse can be transmitted out of any of the following pins: LED_0 (GPIO_0), LED_1 (GPIO_1), or CLKOUT (GPIO_2).
There are two registers that are able to control the routing of the IEEE 1588 transmit and receive indications. The IO_CTRL1 Register 0x0462 – GPIO Control Register #1 is able to route both transmit and receive indications to LED_0 (GPIO_0) and LED_1 (GPIO_1). CLKOUT transmit and receive 1588 SFD indication is found in the IO_CTRL2 Register 0x0463 – GPIO Control Register #2.