SNLS579A April 2018 – November 2018 DP83TC811S-Q1
Wake-on-LAN provides a mechanism to detect specific frames and notify the connected controller through either register status change, GPIO indication or an interrupt flag. WoL within the DP83TC811S-Q1 allows for connected devices residing above the Physical Layer to remain in a low-power state until frames with the qualifying credentials are detected. Supported WoL frame types include: Magic Packet, Magic Packet with Secure-ON, and Custom Pattern Match. When a qualifying WoL frame is received, the DP83TC811S-Q1 WoL logic circuit is able to generate a user defined event (either pulses or level change) through any of the GPIO pins or a status interrupt flag to inform a connected controller that a wake event has occurred. Additionally, the DP83TC811S-Q1 includes a CRC Gate to prevent invalid packets from triggering a wake-up event.
The WoL feature set includes: