SPRSP35G February   2019  – March 2021 DRA829J , DRA829V

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 WKUP Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
        3. 6.3.4.3 WKUP Domain
      5. 6.3.5  I3C
        1. 6.3.5.1 MAIN Domain
        2. 6.3.5.2 MCU Domain
      6. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
        2. 6.3.8.2 MCU Domain
        3. 6.3.8.3 WKUP Domain
      9. 6.3.9  MDIO
        1. 6.3.9.1 MCU Domain
      10. 6.3.10 CPSW2G
        1. 6.3.10.1 MCU Domain
      11. 6.3.11 CPSW9G
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 ECAP
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 EQEP
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 EHRPWM
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 USB
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 SERDES
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 OSPI
        1. 6.3.17.1 MCU Domain
      18. 6.3.18 Hyperbus
        1. 6.3.18.1 MCU Domain
      19. 6.3.19 GPMC
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 MMC
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 CPTS
        1. 6.3.21.1 MAIN Domain
      22. 6.3.22 UFS
        1. 6.3.22.1 MAIN Domain
      23. 6.3.23 PRU_ICSSG [Currently Not Supported]
        1. 6.3.23.1 MAIN Domain
      24. 6.3.24 MCASP
        1. 6.3.24.1 MAIN Domain
      25. 6.3.25 DSS
        1. 6.3.25.1 MAIN Domain
      26. 6.3.26 DP
        1. 6.3.26.1 MAIN Domain
      27. 6.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 6.3.27.1 MAIN Domain
      28. 6.3.28 DSI_TX
        1. 6.3.28.1 MAIN Domain
      29. 6.3.29 VPFE
        1. 6.3.29.1 MAIN Domain
      30. 6.3.30 DMTIMER
        1. 6.3.30.1 MAIN Domain
        2. 6.3.30.2 MCU Domain
      31. 6.3.31 Emulation and Debug
        1. 6.3.31.1 MAIN Domain
      32. 6.3.32 System and Miscellaneous
        1. 6.3.32.1 Boot Mode Configuration
          1. 6.3.32.1.1 MAIN Domain
          2. 6.3.32.1.2 MCU Domain
        2. 6.3.32.2 Clock
          1. 6.3.32.2.1 MAIN Domain
          2. 6.3.32.2.2 WKUP Domain
        3. 6.3.32.3 System
          1. 6.3.32.3.1 MAIN Domain
          2. 6.3.32.3.2 WKUP Domain
        4. 6.3.32.4 EFUSE
      33. 6.3.33 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On-Hour (POH) Limits
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1 USB2PHY Electrical Characteristics
      2. 7.7.2 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      3. 7.7.3 UFS M-PHY Electrical Characteristics
      4. 7.7.4 eDP/DP AUX-PHY Electrical Characteristics
      5. 7.7.5 DDR0 Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics for ALF Package
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Independent MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Independent MCU and Main Domains, Primary Power- Down Sequencing
        6. 7.10.2.6 Entry and Exit of MCU Only State
        7. 7.10.2.7 Entry and Exit of DDR Retention State
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
          6. 7.10.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 7.10.4.1.7 WKUP_LFOSC0 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Device Inputs and Outputs Module Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  VPFE
        3. 7.10.5.3  CPSW2G
          1. 7.10.5.3.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.3.2 CPSW2G RMII Timings
            1. 7.10.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.3.3 CPSW2G RGMII Timings
            1. 7.10.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 7.10.5.4  CPSW9G
          1. 7.10.5.4.1 CPSW9G MDIO Interface Timings
          2. 7.10.5.4.2 CPSW9G RMII Timings
            1. 7.10.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 7.10.5.4.3 CPSW9G RGMII Timings
            1. 7.10.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 7.10.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 7.10.5.5  CSI-2
        6. 7.10.5.6  DDRSS
        7. 7.10.5.7  DSS
        8. 7.10.5.8  eCAP
          1. 7.10.5.8.1 Timing Requirements for eCAP
          2. 7.10.5.8.2 Switching Characteristics for eCAP
        9. 7.10.5.9  EPWM
          1. 7.10.5.9.1 Timing Requirements for eHRPWM
          2. 7.10.5.9.2 Switching Characteristics for eHRPWM
        10. 7.10.5.10 eQEP
          1. 7.10.5.10.1 Timing Requirements for eQEP
          2. 7.10.5.10.2 Switching Characteristics for eQEP
        11. 7.10.5.11 GPIO
          1. 7.10.5.11.1 GPIO Timing Requirements
          2. 7.10.5.11.2 GPIO Switching Characteristics
        12. 7.10.5.12 GPMC
          1. 7.10.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        13. 7.10.5.13 HyperBus
          1. 7.10.5.13.1 Timing Requirements for HyperBus
          2. 7.10.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 7.10.5.14 I2C
        15. 7.10.5.15 I3C
        16. 7.10.5.16 MCAN
        17. 7.10.5.17 MCASP
        18. 7.10.5.18 MCSPI
          1. 7.10.5.18.1 MCSPI — Master Mode
          2. 7.10.5.18.2 MCSPI — Slave Mode
        19. 7.10.5.19 MMCSD
          1. 7.10.5.19.1 MMC0 - eMMC Interface
            1. 7.10.5.19.1.1 Legacy SDR Mode
            2. 7.10.5.19.1.2 High Speed SDR Mode
            3. 7.10.5.19.1.3 High Speed DDR Mode
            4. 7.10.5.19.1.4 HS200 Mode
          2. 7.10.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.19.2.1 Default Speed Mode
            2. 7.10.5.19.2.2 High Speed Mode
            3. 7.10.5.19.2.3 UHS–I SDR12 Mode
            4. 7.10.5.19.2.4 UHS–I SDR25 Mode
            5. 7.10.5.19.2.5 UHS–I SDR50 Mode
            6. 7.10.5.19.2.6 UHS–I DDR50 Mode
        20. 7.10.5.20 CPTS
          1. 7.10.5.20.1 CPTS Timing Requirements
          2. 7.10.5.20.2 CPTS Switching Characteristics
        21. 7.10.5.21 OSPI
          1. 7.10.5.21.1 OSPI With Data Training
            1. 7.10.5.21.1.1 OSPI Switching Characteristics – Data Training
          2. 7.10.5.21.2 OSPI Without Data Training
            1. 7.10.5.21.2.1 OSPI Switching Characteristics – DDR Mode
            2. 7.10.5.21.2.2 OSPI Switching Characteristics – SDR Mode
            3. 7.10.5.21.2.3 OSPI Timing Requirements – DDR Mode
            4. 7.10.5.21.2.4 OSPI Timing Requirements – SDR Mode
        22. 7.10.5.22 OLDI
          1. 7.10.5.22.1 OLDI Switching Characteristics
        23. 7.10.5.23 PCIE
        24. 7.10.5.24 Timers
          1. 7.10.5.24.1 Timing Requirements for Timers
          2. 7.10.5.24.2 Switching Characteristics for Timers
        25. 7.10.5.25 UART
          1. 7.10.5.25.1 Timing Requirements for UART
          2. 7.10.5.25.2 UART Switching Characteristics
        26. 7.10.5.26 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
      3. 8.2.3 DSP C71x
      4. 8.2.4 DSP C66x
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 GPU
      2. 8.3.2 D5520MP2
      3. 8.3.3 VXE384MP2
    4. 8.4 Other Subsystems
      1. 8.4.1 MSMC
      2. 8.4.2 NAVSS
        1. 8.4.2.1 NAVSS0
        2. 8.4.2.2 MCU_NAVSS
        3. 8.4.2.3
      3. 8.4.3 PDMA Controller
      4. 8.4.4 Peripherals
        1. 8.4.4.1  ADC
        2. 8.4.4.2  ATL
        3. 8.4.4.3  CSI
          1. 8.4.4.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 8.4.4.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 8.4.4.4  CPSW2G
        5. 8.4.4.5  CPSW9G
        6. 8.4.4.6  DCC
        7. 8.4.4.7  DDRSS
        8. 8.4.4.8  DSS
          1. 8.4.4.8.1 DSI
          2. 8.4.4.8.2 eDP
        9. 8.4.4.9  VPFE
        10. 8.4.4.10 eCAP
        11. 8.4.4.11 EPWM
        12. 8.4.4.12 ELM
        13. 8.4.4.13 ESM
        14. 8.4.4.14 eQEP
        15. 8.4.4.15 GPIO
        16. 8.4.4.16 GPMC
        17. 8.4.4.17 Hyperbus
        18. 8.4.4.18 I2C
        19. 8.4.4.19 I3C
        20. 8.4.4.20 MCAN
        21. 8.4.4.21 MCASP
        22. 8.4.4.22 MCRC Controller
        23. 8.4.4.23 MCSPI
        24. 8.4.4.24 MMC/SD
        25. 8.4.4.25 OSPI
        26. 8.4.4.26 PCIE
        27. 8.4.4.27 SerDes
        28. 8.4.4.28 WWDT
        29. 8.4.4.29 Timers
        30. 8.4.4.30 UART
        31. 8.4.4.31 USB
        32. 8.4.4.32 UFS
  9. Applications and Implementation
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide for AM752x/DRA829/TDA4VM Devices
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 SERDES REFCLK Design Guidelines
      4. 9.3.4 USB VBUS Design Guidelines
      5. 9.3.5 System Power Supply Monitor Design Guidelines
      6. 9.3.6 High Speed Differential Signal Routing Guidance
      7. 9.3.7 External Capacitors
      8. 9.3.8 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ALF|827
サーマルパッド・メカニカル・データ
発注情報

MAIN Domain

Table 6-92 PRU_ICSSG0 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
PRG0_ECAP0_IN_APWM_OUTPRU_ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) OuputIOAB29
PRG0_ECAP0_SYNC_INPRU_ICSSG ECAP Sync InputIAC28
PRG0_ECAP0_SYNC_OUTPRU_ICSSG ECAP Sync OutputOAB24
PRG0_IEP0_EDIO_OUTVALIDPRU_ICSSG Industrial Ethernet Digital I/O OutvalidOY3
PRG0_IEP0_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAB29, Y3
PRG0_IEP0_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAC28, P23
PRG0_IEP0_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAB28, Y1
PRG0_IEP0_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAB24, R28
PRG0_IEP0_EDIO_DATA_IN_OUT28PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAB26
PRG0_IEP0_EDIO_DATA_IN_OUT29PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAB25
PRG0_IEP0_EDIO_DATA_IN_OUT30PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOY24
PRG0_IEP0_EDIO_DATA_IN_OUT31PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAA25
PRG0_IEP1_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAA26, Y5
PRG0_IEP1_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAA24, T27
PRG0_IEP1_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAA29, Y2
PRG0_IEP1_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOT24, Y25
PRG0_MDIO0_MDCPRU_ICSSG MDIO ClockOAA27
PRG0_MDIO0_MDIOPRU_ICSSG MDIO DataIOY26
PRG0_PRU0_GPI0PRU_ICSSG PRU Data InputIAF28
PRG0_PRU0_GPI1PRU_ICSSG PRU Data InputIAE28
PRG0_PRU0_GPI2PRU_ICSSG PRU Data InputIAE27
PRG0_PRU0_GPI3PRU_ICSSG PRU Data InputIAD26
PRG0_PRU0_GPI4PRU_ICSSG PRU Data InputIAD25
PRG0_PRU0_GPI5PRU_ICSSG PRU Data InputIAC29
PRG0_PRU0_GPI6PRU_ICSSG PRU Data InputIAE26
PRG0_PRU0_GPI7PRU_ICSSG PRU Data InputIAC28
PRG0_PRU0_GPI8PRU_ICSSG PRU Data InputIAC27
PRG0_PRU0_GPI9PRU_ICSSG PRU Data InputIAB26
PRG0_PRU0_GPI10PRU_ICSSG PRU Data InputIAB25
PRG0_PRU0_GPI11PRU_ICSSG PRU Data InputIAJ28
PRG0_PRU0_GPI12PRU_ICSSG PRU Data InputIAH27
PRG0_PRU0_GPI13PRU_ICSSG PRU Data InputIAH29
PRG0_PRU0_GPI14PRU_ICSSG PRU Data InputIAG28
PRG0_PRU0_GPI15PRU_ICSSG PRU Data InputIAG27
PRG0_PRU0_GPI16PRU_ICSSG PRU Data InputIAH28
PRG0_PRU0_GPI17PRU_ICSSG PRU Data InputIAB24
PRG0_PRU0_GPI18PRU_ICSSG PRU Data InputIAB29
PRG0_PRU0_GPI19PRU_ICSSG PRU Data InputIAB28
PRG0_PRU0_GPO0PRU_ICSSG PRU Data OutputIOAF28
PRG0_PRU0_GPO1PRU_ICSSG PRU Data OutputIOAE28
PRG0_PRU0_GPO2PRU_ICSSG PRU Data OutputIOAE27
PRG0_PRU0_GPO3PRU_ICSSG PRU Data OutputIOAD26
PRG0_PRU0_GPO4PRU_ICSSG PRU Data OutputIOAD25
PRG0_PRU0_GPO5PRU_ICSSG PRU Data OutputIOAC29
PRG0_PRU0_GPO6PRU_ICSSG PRU Data OutputIOAE26
PRG0_PRU0_GPO7PRU_ICSSG PRU Data OutputIOAC28
PRG0_PRU0_GPO8PRU_ICSSG PRU Data OutputIOAC27
PRG0_PRU0_GPO9PRU_ICSSG PRU Data OutputIOAB26
PRG0_PRU0_GPO10PRU_ICSSG PRU Data OutputIOAB25
PRG0_PRU0_GPO11PRU_ICSSG PRU Data OutputIOAJ28
PRG0_PRU0_GPO12PRU_ICSSG PRU Data OutputIOAH27
PRG0_PRU0_GPO13PRU_ICSSG PRU Data OutputIOAH29
PRG0_PRU0_GPO14PRU_ICSSG PRU Data OutputIOAG28
PRG0_PRU0_GPO15PRU_ICSSG PRU Data OutputIOAG27
PRG0_PRU0_GPO16PRU_ICSSG PRU Data OutputIOAH28
PRG0_PRU0_GPO17PRU_ICSSG PRU Data OutputIOAB24
PRG0_PRU0_GPO18PRU_ICSSG PRU Data OutputIOAB29
PRG0_PRU0_GPO19PRU_ICSSG PRU Data OutputIOAB28
PRG0_PRU1_GPI0PRU_ICSSG PRU Data InputIAE29
PRG0_PRU1_GPI1PRU_ICSSG PRU Data InputIAD28
PRG0_PRU1_GPI2PRU_ICSSG PRU Data InputIAD27
PRG0_PRU1_GPI3PRU_ICSSG PRU Data InputIAC25
PRG0_PRU1_GPI4PRU_ICSSG PRU Data InputIAD29
PRG0_PRU1_GPI5PRU_ICSSG PRU Data InputIAB27
PRG0_PRU1_GPI6PRU_ICSSG PRU Data InputIAC26
PRG0_PRU1_GPI7PRU_ICSSG PRU Data InputIAA24
PRG0_PRU1_GPI8PRU_ICSSG PRU Data InputIAA28
PRG0_PRU1_GPI9PRU_ICSSG PRU Data InputIY24
PRG0_PRU1_GPI10PRU_ICSSG PRU Data InputIAA25
PRG0_PRU1_GPI11PRU_ICSSG PRU Data InputIAG26
PRG0_PRU1_GPI12PRU_ICSSG PRU Data InputIAF27
PRG0_PRU1_GPI13PRU_ICSSG PRU Data InputIAF26
PRG0_PRU1_GPI14PRU_ICSSG PRU Data InputIAE25
PRG0_PRU1_GPI15PRU_ICSSG PRU Data InputIAF29
PRG0_PRU1_GPI16PRU_ICSSG PRU Data InputIAG29
PRG0_PRU1_GPI17PRU_ICSSG PRU Data InputIY25
PRG0_PRU1_GPI18PRU_ICSSG PRU Data InputIAA26
PRG0_PRU1_GPI19PRU_ICSSG PRU Data InputIAA29
PRG0_PRU1_GPO0PRU_ICSSG PRU Data OutputIOAE29
PRG0_PRU1_GPO1PRU_ICSSG PRU Data OutputIOAD28
PRG0_PRU1_GPO2PRU_ICSSG PRU Data OutputIOAD27
PRG0_PRU1_GPO3PRU_ICSSG PRU Data OutputIOAC25
PRG0_PRU1_GPO4PRU_ICSSG PRU Data OutputIOAD29
PRG0_PRU1_GPO5PRU_ICSSG PRU Data OutputIOAB27
PRG0_PRU1_GPO6PRU_ICSSG PRU Data OutputIOAC26
PRG0_PRU1_GPO7PRU_ICSSG PRU Data OutputIOAA24
PRG0_PRU1_GPO8PRU_ICSSG PRU Data OutputIOAA28
PRG0_PRU1_GPO9PRU_ICSSG PRU Data OutputIOY24
PRG0_PRU1_GPO10PRU_ICSSG PRU Data OutputIOAA25
PRG0_PRU1_GPO11PRU_ICSSG PRU Data OutputIOAG26
PRG0_PRU1_GPO12PRU_ICSSG PRU Data OutputIOAF27
PRG0_PRU1_GPO13PRU_ICSSG PRU Data OutputIOAF26
PRG0_PRU1_GPO14PRU_ICSSG PRU Data OutputIOAE25
PRG0_PRU1_GPO15PRU_ICSSG PRU Data OutputIOAF29
PRG0_PRU1_GPO16PRU_ICSSG PRU Data OutputIOAG29
PRG0_PRU1_GPO17PRU_ICSSG PRU Data OutputIOY25
PRG0_PRU1_GPO18PRU_ICSSG PRU Data OutputIOAA26
PRG0_PRU1_GPO19PRU_ICSSG PRU Data OutputIOAA29
PRG0_PWM0_TZ_INPRU_ICSSG PWM Trip Zone InputIAB29
PRG0_PWM0_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAB28
PRG0_PWM1_TZ_INPRU_ICSSG PWM Trip Zone InputIAA26
PRG0_PWM1_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAA29
PRG0_PWM2_TZ_INPRU_ICSSG PWM Trip Zone InputIAA25
PRG0_PWM2_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAA28
PRG0_PWM3_TZ_INPRU_ICSSG PWM Trip Zone InputIAB26
PRG0_PWM3_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAJ28
PRG0_PWM0_A0PRU_ICSSG PWM Output AIOAH27
PRG0_PWM0_A1PRU_ICSSG PWM Output AIOAG28
PRG0_PWM0_A2PRU_ICSSG PWM Output AIOAH28
PRG0_PWM0_B0PRU_ICSSG PWM Output BIOAH29
PRG0_PWM0_B1PRU_ICSSG PWM Output BIOAG27
PRG0_PWM0_B2PRU_ICSSG PWM Output BIOAB24
PRG0_PWM1_A0PRU_ICSSG PWM Output AIOAF27
PRG0_PWM1_A1PRU_ICSSG PWM Output AIOAE25
PRG0_PWM1_A2PRU_ICSSG PWM Output AIOAG29
PRG0_PWM1_B0PRU_ICSSG PWM Output BIOAF26
PRG0_PWM1_B1PRU_ICSSG PWM Output BIOAF29
PRG0_PWM1_B2PRU_ICSSG PWM Output BIOY25
PRG0_PWM2_A0PRU_ICSSG PWM Output AIOAE27
PRG0_PWM2_A1PRU_ICSSG PWM Output AIOAC27
PRG0_PWM2_A2PRU_ICSSG PWM Output AIOAD27
PRG0_PWM2_B0PRU_ICSSG PWM Output BIOAD25
PRG0_PWM2_B1PRU_ICSSG PWM Output BIOAB25
PRG0_PWM2_B2PRU_ICSSG PWM Output BIOAD29
PRG0_PWM3_A0PRU_ICSSG PWM Output AIOAF28
PRG0_PWM3_A1PRU_ICSSG PWM Output AIOAE26
PRG0_PWM3_A2PRU_ICSSG PWM Output AIOAD26
PRG0_PWM3_B0PRU_ICSSG PWM Output BIOAE28
PRG0_PWM3_B1PRU_ICSSG PWM Output BIOAC28
PRG0_PWM3_B2PRU_ICSSG PWM Output BIOAC29
PRG0_RGMII1_RXCPRU_ICSSG RGMII Receive ClockIAE26
PRG0_RGMII1_RX_CTLPRU_ICSSG RGMII Receive ControlIAD25
PRG0_RGMII1_TXCPRU_ICSSG RGMII Transmit ClockIOAH28
PRG0_RGMII1_TX_CTLPRU_ICSSG RGMII Transmit ControlOAG27
PRG0_RGMII2_RXCPRU_ICSSG RGMII Receive ClockIAC26
PRG0_RGMII2_RX_CTLPRU_ICSSG RGMII Receive ControlIAD29
PRG0_RGMII2_TXCPRU_ICSSG RGMII Transmit ClockIOAG29
PRG0_RGMII2_TX_CTLPRU_ICSSG RGMII Transmit ControlOAF29
PRG0_RGMII1_RD0PRU_ICSSG RGMII Receive DataIAF28
PRG0_RGMII1_RD1PRU_ICSSG RGMII Receive DataIAE28
PRG0_RGMII1_RD2PRU_ICSSG RGMII Receive DataIAE27
PRG0_RGMII1_RD3PRU_ICSSG RGMII Receive DataIAD26
PRG0_RGMII1_TD0PRU_ICSSG RGMII Transmit DataOAJ28
PRG0_RGMII1_TD1PRU_ICSSG RGMII Transmit DataOAH27
PRG0_RGMII1_TD2PRU_ICSSG RGMII Transmit DataOAH29
PRG0_RGMII1_TD3PRU_ICSSG RGMII Transmit DataOAG28
PRG0_RGMII2_RD0PRU_ICSSG RGMII Receive DataIAE29
PRG0_RGMII2_RD1PRU_ICSSG RGMII Receive DataIAD28
PRG0_RGMII2_RD2PRU_ICSSG RGMII Receive DataIAD27
PRG0_RGMII2_RD3PRU_ICSSG RGMII Receive DataIAC25
PRG0_RGMII2_TD0PRU_ICSSG RGMII Transmit DataOAG26
PRG0_RGMII2_TD1PRU_ICSSG RGMII Transmit DataOAF27
PRG0_RGMII2_TD2PRU_ICSSG RGMII Transmit DataOAF26
PRG0_RGMII2_TD3PRU_ICSSG RGMII Transmit DataOAE25
PRG0_UART0_CTSnPRU_ICSSG UART Clear to Send (active low)IAB26
PRG0_UART0_RTSnPRU_ICSSG UART Request to Send (active low)OAB25
PRG0_UART0_RXDPRU_ICSSG UART Receive DataIY24
PRG0_UART0_TXDPRU_ICSSG UART Transmit DataOAA25
Table 6-93 PRU_ICSSG1 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
PRG1_ECAP0_IN_APWM_OUTPRU_ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) OuputIOAH22
PRG1_ECAP0_SYNC_INPRU_ICSSG ECAP Sync InputIAJ22
PRG1_ECAP0_SYNC_OUTPRU_ICSSG ECAP Sync OutputOAC22
PRG1_IEP0_EDIO_OUTVALIDPRU_ICSSG Industrial Ethernet Digital I/O OutvalidOY4
PRG1_IEP0_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAE21
PRG1_IEP0_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAE20
PRG1_IEP0_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAH21
PRG1_IEP0_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAJ21
PRG1_IEP0_EDIO_DATA_IN_OUT28PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAG20
PRG1_IEP0_EDIO_DATA_IN_OUT29PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAD21
PRG1_IEP0_EDIO_DATA_IN_OUT30PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAF21
PRG1_IEP0_EDIO_DATA_IN_OUT31PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAB23
PRG1_IEP1_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAJ22
PRG1_IEP1_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAC21
PRG1_IEP1_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAH22
PRG1_IEP1_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAC22
PRG1_MDIO0_MDCPRU_ICSSG MDIO ClockOAD18
PRG1_MDIO0_MDIOPRU_ICSSG MDIO DataIOAD19
PRG1_PRU0_GPI0PRU_ICSSG PRU Data InputIAC23
PRG1_PRU0_GPI1PRU_ICSSG PRU Data InputIAG22
PRG1_PRU0_GPI2PRU_ICSSG PRU Data InputIAF22
PRG1_PRU0_GPI3PRU_ICSSG PRU Data InputIAJ23
PRG1_PRU0_GPI4PRU_ICSSG PRU Data InputIAH23
PRG1_PRU0_GPI5PRU_ICSSG PRU Data InputIAD20
PRG1_PRU0_GPI6PRU_ICSSG PRU Data InputIAD22
PRG1_PRU0_GPI7PRU_ICSSG PRU Data InputIAE20
PRG1_PRU0_GPI8PRU_ICSSG PRU Data InputIAJ20
PRG1_PRU0_GPI9PRU_ICSSG PRU Data InputIAG20
PRG1_PRU0_GPI10PRU_ICSSG PRU Data InputIAD21
PRG1_PRU0_GPI11PRU_ICSSG PRU Data InputIAF24
PRG1_PRU0_GPI12PRU_ICSSG PRU Data InputIAJ24
PRG1_PRU0_GPI13PRU_ICSSG PRU Data InputIAG24
PRG1_PRU0_GPI14PRU_ICSSG PRU Data InputIAD24
PRG1_PRU0_GPI15PRU_ICSSG PRU Data InputIAC24
PRG1_PRU0_GPI16PRU_ICSSG PRU Data InputIAE24
PRG1_PRU0_GPI17PRU_ICSSG PRU Data InputIAJ21
PRG1_PRU0_GPI18PRU_ICSSG PRU Data InputIAE21
PRG1_PRU0_GPI19PRU_ICSSG PRU Data InputIAH21
PRG1_PRU0_GPO0PRU_ICSSG PRU Data OutputIOAC23
PRG1_PRU0_GPO1PRU_ICSSG PRU Data OutputIOAG22
PRG1_PRU0_GPO2PRU_ICSSG PRU Data OutputIOAF22
PRG1_PRU0_GPO3PRU_ICSSG PRU Data OutputIOAJ23
PRG1_PRU0_GPO4PRU_ICSSG PRU Data OutputIOAH23
PRG1_PRU0_GPO5PRU_ICSSG PRU Data OutputIOAD20
PRG1_PRU0_GPO6PRU_ICSSG PRU Data OutputIOAD22
PRG1_PRU0_GPO7PRU_ICSSG PRU Data OutputIOAE20
PRG1_PRU0_GPO8PRU_ICSSG PRU Data OutputIOAJ20
PRG1_PRU0_GPO9PRU_ICSSG PRU Data OutputIOAG20
PRG1_PRU0_GPO10PRU_ICSSG PRU Data OutputIOAD21
PRG1_PRU0_GPO11PRU_ICSSG PRU Data OutputIOAF24
PRG1_PRU0_GPO12PRU_ICSSG PRU Data OutputIOAJ24
PRG1_PRU0_GPO13PRU_ICSSG PRU Data OutputIOAG24
PRG1_PRU0_GPO14PRU_ICSSG PRU Data OutputIOAD24
PRG1_PRU0_GPO15PRU_ICSSG PRU Data OutputIOAC24
PRG1_PRU0_GPO16PRU_ICSSG PRU Data OutputIOAE24
PRG1_PRU0_GPO17PRU_ICSSG PRU Data OutputIOAJ21
PRG1_PRU0_GPO18PRU_ICSSG PRU Data OutputIOAE21
PRG1_PRU0_GPO19PRU_ICSSG PRU Data OutputIOAH21
PRG1_PRU1_GPI0PRU_ICSSG PRU Data InputIAE22
PRG1_PRU1_GPI1PRU_ICSSG PRU Data InputIAG23
PRG1_PRU1_GPI2PRU_ICSSG PRU Data InputIAF23
PRG1_PRU1_GPI3PRU_ICSSG PRU Data InputIAD23
PRG1_PRU1_GPI4PRU_ICSSG PRU Data InputIAH24
PRG1_PRU1_GPI5PRU_ICSSG PRU Data InputIAG21
PRG1_PRU1_GPI6PRU_ICSSG PRU Data InputIAE23
PRG1_PRU1_GPI7PRU_ICSSG PRU Data InputIAC21
PRG1_PRU1_GPI8PRU_ICSSG PRU Data InputIY23
PRG1_PRU1_GPI9PRU_ICSSG PRU Data InputIAF21
PRG1_PRU1_GPI10PRU_ICSSG PRU Data InputIAB23
PRG1_PRU1_GPI11PRU_ICSSG PRU Data InputIAJ25
PRG1_PRU1_GPI12PRU_ICSSG PRU Data InputIAH25
PRG1_PRU1_GPI13PRU_ICSSG PRU Data InputIAG25
PRG1_PRU1_GPI14PRU_ICSSG PRU Data InputIAH26
PRG1_PRU1_GPI15PRU_ICSSG PRU Data InputIAJ27
PRG1_PRU1_GPI16PRU_ICSSG PRU Data InputIAJ26
PRG1_PRU1_GPI17PRU_ICSSG PRU Data InputIAC22
PRG1_PRU1_GPI18PRU_ICSSG PRU Data InputIAJ22
PRG1_PRU1_GPI19PRU_ICSSG PRU Data InputIAH22
PRG1_PRU1_GPO0PRU_ICSSG PRU Data OutputIOAE22
PRG1_PRU1_GPO1PRU_ICSSG PRU Data OutputIOAG23
PRG1_PRU1_GPO2PRU_ICSSG PRU Data OutputIOAF23
PRG1_PRU1_GPO3PRU_ICSSG PRU Data OutputIOAD23
PRG1_PRU1_GPO4PRU_ICSSG PRU Data OutputIOAH24
PRG1_PRU1_GPO5PRU_ICSSG PRU Data OutputIOAG21
PRG1_PRU1_GPO6PRU_ICSSG PRU Data OutputIOAE23
PRG1_PRU1_GPO7PRU_ICSSG PRU Data OutputIOAC21
PRG1_PRU1_GPO8PRU_ICSSG PRU Data OutputIOY23
PRG1_PRU1_GPO9PRU_ICSSG PRU Data OutputIOAF21
PRG1_PRU1_GPO10PRU_ICSSG PRU Data OutputIOAB23
PRG1_PRU1_GPO11PRU_ICSSG PRU Data OutputIOAJ25
PRG1_PRU1_GPO12PRU_ICSSG PRU Data OutputIOAH25
PRG1_PRU1_GPO13PRU_ICSSG PRU Data OutputIOAG25
PRG1_PRU1_GPO14PRU_ICSSG PRU Data OutputIOAH26
PRG1_PRU1_GPO15PRU_ICSSG PRU Data OutputIOAJ27
PRG1_PRU1_GPO16PRU_ICSSG PRU Data OutputIOAJ26
PRG1_PRU1_GPO17PRU_ICSSG PRU Data OutputIOAC22
PRG1_PRU1_GPO18PRU_ICSSG PRU Data OutputIOAJ22
PRG1_PRU1_GPO19PRU_ICSSG PRU Data OutputIOAH22
PRG1_PWM0_TZ_INPRU_ICSSG PWM Trip Zone InputIAE21
PRG1_PWM0_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAH21
PRG1_PWM1_TZ_INPRU_ICSSG PWM Trip Zone InputIAJ22
PRG1_PWM1_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAH22
PRG1_PWM2_TZ_INPRU_ICSSG PWM Trip Zone InputIAB23
PRG1_PWM2_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOY23
PRG1_PWM3_TZ_INPRU_ICSSG PWM Trip Zone InputIAG20
PRG1_PWM3_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAF24
PRG1_PWM0_A0PRU_ICSSG PWM Output AIOAJ24
PRG1_PWM0_A1PRU_ICSSG PWM Output AIOAD24
PRG1_PWM0_A2PRU_ICSSG PWM Output AIOAE24
PRG1_PWM0_B0PRU_ICSSG PWM Output BIOAG24
PRG1_PWM0_B1PRU_ICSSG PWM Output BIOAC24
PRG1_PWM0_B2PRU_ICSSG PWM Output BIOAJ21
PRG1_PWM1_A0PRU_ICSSG PWM Output AIOAH25
PRG1_PWM1_A1PRU_ICSSG PWM Output AIOAH26
PRG1_PWM1_A2PRU_ICSSG PWM Output AIOAJ26
PRG1_PWM1_B0PRU_ICSSG PWM Output BIOAG25
PRG1_PWM1_B1PRU_ICSSG PWM Output BIOAJ27
PRG1_PWM1_B2PRU_ICSSG PWM Output BIOAC22
PRG1_PWM2_A0PRU_ICSSG PWM Output AIOAF22
PRG1_PWM2_A1PRU_ICSSG PWM Output AIOAJ20
PRG1_PWM2_A2PRU_ICSSG PWM Output AIOAF23
PRG1_PWM2_B0PRU_ICSSG PWM Output BIOAH23
PRG1_PWM2_B1PRU_ICSSG PWM Output BIOAD21
PRG1_PWM2_B2PRU_ICSSG PWM Output BIOAH24
PRG1_PWM3_A0PRU_ICSSG PWM Output AIOAC23
PRG1_PWM3_A1PRU_ICSSG PWM Output AIOAD22
PRG1_PWM3_A2PRU_ICSSG PWM Output AIOAJ23
PRG1_PWM3_B0PRU_ICSSG PWM Output BIOAG22
PRG1_PWM3_B1PRU_ICSSG PWM Output BIOAE20
PRG1_PWM3_B2PRU_ICSSG PWM Output BIOAD20
PRG1_RGMII1_RXCPRU_ICSSG RGMII Receive ClockIAD22
PRG1_RGMII1_RX_CTLPRU_ICSSG RGMII Receive ControlIAH23
PRG1_RGMII1_TXCPRU_ICSSG RGMII Transmit ClockIOAE24
PRG1_RGMII1_TX_CTLPRU_ICSSG RGMII Transmit ControlOAC24
PRG1_RGMII2_RXCPRU_ICSSG RGMII Receive ClockIAE23
PRG1_RGMII2_RX_CTLPRU_ICSSG RGMII Receive ControlIAH24
PRG1_RGMII2_TXCPRU_ICSSG RGMII Transmit ClockIOAJ26
PRG1_RGMII2_TX_CTLPRU_ICSSG RGMII Transmit ControlOAJ27
PRG1_RGMII1_RD0PRU_ICSSG RGMII Receive DataIAC23
PRG1_RGMII1_RD1PRU_ICSSG RGMII Receive DataIAG22
PRG1_RGMII1_RD2PRU_ICSSG RGMII Receive DataIAF22
PRG1_RGMII1_RD3PRU_ICSSG RGMII Receive DataIAJ23
PRG1_RGMII1_TD0PRU_ICSSG RGMII Transmit DataOAF24
PRG1_RGMII1_TD1PRU_ICSSG RGMII Transmit DataOAJ24
PRG1_RGMII1_TD2PRU_ICSSG RGMII Transmit DataOAG24
PRG1_RGMII1_TD3PRU_ICSSG RGMII Transmit DataOAD24
PRG1_RGMII2_RD0PRU_ICSSG RGMII Receive DataIAE22
PRG1_RGMII2_RD1PRU_ICSSG RGMII Receive DataIAG23
PRG1_RGMII2_RD2PRU_ICSSG RGMII Receive DataIAF23
PRG1_RGMII2_RD3PRU_ICSSG RGMII Receive DataIAD23
PRG1_RGMII2_TD0PRU_ICSSG RGMII Transmit DataOAJ25
PRG1_RGMII2_TD1PRU_ICSSG RGMII Transmit DataOAH25
PRG1_RGMII2_TD2PRU_ICSSG RGMII Transmit DataOAG25
PRG1_RGMII2_TD3PRU_ICSSG RGMII Transmit DataOAH26
PRG1_UART0_CTSnPRU_ICSSG UART Clear to Send (active low)IAG20
PRG1_UART0_RTSnPRU_ICSSG UART Request to Send (active low)OAD21
PRG1_UART0_RXDPRU_ICSSG UART Receive DataIAF21
PRG1_UART0_TXDPRU_ICSSG UART Transmit DataOAB23