The supported features by the device EPWM are:
- Dedicated 16-bit time-base counter with period and frequency control
- Two independent PWM outputs which can be used in different configurations (with single-edge operation, with dual-edge symmetric operation or one independent PWM output with dual-edge asymmetric operation)
- Asynchronous override control of PWM signals during fault conditions
- Programmable phase-control support for lag or lead operation relative to other EPWM modules
- Dead-band generation with independent rising and falling edge delay control
- Programmable trip zone allocation of both latched and un-latched fault conditions
- Events enabling to trigger both CPU interrupts and start of ADC conversions
Table 7-52 represents EPWM timing conditions.
Table 7-52 EPWM Timing Conditions
||Input slew rate
||Output load capacitance
Section 220.127.116.11.2, Section 18.104.22.168.1 and present timing and switching characteristics for eHRPWM (see Figure 7-58, Figure 7-59, Figure 7-60, and Figure 7-57).