SPRSP35G February   2019  – March 2021 DRA829J , DRA829V

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 WKUP Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
        3. 6.3.4.3 WKUP Domain
      5. 6.3.5  I3C
        1. 6.3.5.1 MAIN Domain
        2. 6.3.5.2 MCU Domain
      6. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
        2. 6.3.8.2 MCU Domain
        3. 6.3.8.3 WKUP Domain
      9. 6.3.9  MDIO
        1. 6.3.9.1 MCU Domain
      10. 6.3.10 CPSW2G
        1. 6.3.10.1 MCU Domain
      11. 6.3.11 CPSW9G
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 ECAP
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 EQEP
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 EHRPWM
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 USB
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 SERDES
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 OSPI
        1. 6.3.17.1 MCU Domain
      18. 6.3.18 Hyperbus
        1. 6.3.18.1 MCU Domain
      19. 6.3.19 GPMC
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 MMC
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 CPTS
        1. 6.3.21.1 MAIN Domain
      22. 6.3.22 UFS
        1. 6.3.22.1 MAIN Domain
      23. 6.3.23 PRU_ICSSG [Currently Not Supported]
        1. 6.3.23.1 MAIN Domain
      24. 6.3.24 MCASP
        1. 6.3.24.1 MAIN Domain
      25. 6.3.25 DSS
        1. 6.3.25.1 MAIN Domain
      26. 6.3.26 DP
        1. 6.3.26.1 MAIN Domain
      27. 6.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 6.3.27.1 MAIN Domain
      28. 6.3.28 DSI_TX
        1. 6.3.28.1 MAIN Domain
      29. 6.3.29 VPFE
        1. 6.3.29.1 MAIN Domain
      30. 6.3.30 DMTIMER
        1. 6.3.30.1 MAIN Domain
        2. 6.3.30.2 MCU Domain
      31. 6.3.31 Emulation and Debug
        1. 6.3.31.1 MAIN Domain
      32. 6.3.32 System and Miscellaneous
        1. 6.3.32.1 Boot Mode Configuration
          1. 6.3.32.1.1 MAIN Domain
          2. 6.3.32.1.2 MCU Domain
        2. 6.3.32.2 Clock
          1. 6.3.32.2.1 MAIN Domain
          2. 6.3.32.2.2 WKUP Domain
        3. 6.3.32.3 System
          1. 6.3.32.3.1 MAIN Domain
          2. 6.3.32.3.2 WKUP Domain
        4. 6.3.32.4 EFUSE
      33. 6.3.33 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On-Hour (POH) Limits
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1 USB2PHY Electrical Characteristics
      2. 7.7.2 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      3. 7.7.3 UFS M-PHY Electrical Characteristics
      4. 7.7.4 eDP/DP AUX-PHY Electrical Characteristics
      5. 7.7.5 DDR0 Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics for ALF Package
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Independent MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Independent MCU and Main Domains, Primary Power- Down Sequencing
        6. 7.10.2.6 Entry and Exit of MCU Only State
        7. 7.10.2.7 Entry and Exit of DDR Retention State
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
          6. 7.10.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 7.10.4.1.7 WKUP_LFOSC0 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Device Inputs and Outputs Module Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  VPFE
        3. 7.10.5.3  CPSW2G
          1. 7.10.5.3.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.3.2 CPSW2G RMII Timings
            1. 7.10.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.3.3 CPSW2G RGMII Timings
            1. 7.10.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 7.10.5.4  CPSW9G
          1. 7.10.5.4.1 CPSW9G MDIO Interface Timings
          2. 7.10.5.4.2 CPSW9G RMII Timings
            1. 7.10.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 7.10.5.4.3 CPSW9G RGMII Timings
            1. 7.10.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 7.10.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 7.10.5.5  CSI-2
        6. 7.10.5.6  DDRSS
        7. 7.10.5.7  DSS
        8. 7.10.5.8  eCAP
          1. 7.10.5.8.1 Timing Requirements for eCAP
          2. 7.10.5.8.2 Switching Characteristics for eCAP
        9. 7.10.5.9  EPWM
          1. 7.10.5.9.1 Timing Requirements for eHRPWM
          2. 7.10.5.9.2 Switching Characteristics for eHRPWM
        10. 7.10.5.10 eQEP
          1. 7.10.5.10.1 Timing Requirements for eQEP
          2. 7.10.5.10.2 Switching Characteristics for eQEP
        11. 7.10.5.11 GPIO
          1. 7.10.5.11.1 GPIO Timing Requirements
          2. 7.10.5.11.2 GPIO Switching Characteristics
        12. 7.10.5.12 GPMC
          1. 7.10.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        13. 7.10.5.13 HyperBus
          1. 7.10.5.13.1 Timing Requirements for HyperBus
          2. 7.10.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 7.10.5.14 I2C
        15. 7.10.5.15 I3C
        16. 7.10.5.16 MCAN
        17. 7.10.5.17 MCASP
        18. 7.10.5.18 MCSPI
          1. 7.10.5.18.1 MCSPI — Master Mode
          2. 7.10.5.18.2 MCSPI — Slave Mode
        19. 7.10.5.19 MMCSD
          1. 7.10.5.19.1 MMC0 - eMMC Interface
            1. 7.10.5.19.1.1 Legacy SDR Mode
            2. 7.10.5.19.1.2 High Speed SDR Mode
            3. 7.10.5.19.1.3 High Speed DDR Mode
            4. 7.10.5.19.1.4 HS200 Mode
          2. 7.10.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.19.2.1 Default Speed Mode
            2. 7.10.5.19.2.2 High Speed Mode
            3. 7.10.5.19.2.3 UHS–I SDR12 Mode
            4. 7.10.5.19.2.4 UHS–I SDR25 Mode
            5. 7.10.5.19.2.5 UHS–I SDR50 Mode
            6. 7.10.5.19.2.6 UHS–I DDR50 Mode
        20. 7.10.5.20 CPTS
          1. 7.10.5.20.1 CPTS Timing Requirements
          2. 7.10.5.20.2 CPTS Switching Characteristics
        21. 7.10.5.21 OSPI
          1. 7.10.5.21.1 OSPI With Data Training
            1. 7.10.5.21.1.1 OSPI Switching Characteristics – Data Training
          2. 7.10.5.21.2 OSPI Without Data Training
            1. 7.10.5.21.2.1 OSPI Switching Characteristics – DDR Mode
            2. 7.10.5.21.2.2 OSPI Switching Characteristics – SDR Mode
            3. 7.10.5.21.2.3 OSPI Timing Requirements – DDR Mode
            4. 7.10.5.21.2.4 OSPI Timing Requirements – SDR Mode
        22. 7.10.5.22 OLDI
          1. 7.10.5.22.1 OLDI Switching Characteristics
        23. 7.10.5.23 PCIE
        24. 7.10.5.24 Timers
          1. 7.10.5.24.1 Timing Requirements for Timers
          2. 7.10.5.24.2 Switching Characteristics for Timers
        25. 7.10.5.25 UART
          1. 7.10.5.25.1 Timing Requirements for UART
          2. 7.10.5.25.2 UART Switching Characteristics
        26. 7.10.5.26 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
      3. 8.2.3 DSP C71x
      4. 8.2.4 DSP C66x
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 GPU
      2. 8.3.2 D5520MP2
      3. 8.3.3 VXE384MP2
    4. 8.4 Other Subsystems
      1. 8.4.1 MSMC
      2. 8.4.2 NAVSS
        1. 8.4.2.1 NAVSS0
        2. 8.4.2.2 MCU_NAVSS
        3. 8.4.2.3
      3. 8.4.3 PDMA Controller
      4. 8.4.4 Peripherals
        1. 8.4.4.1  ADC
        2. 8.4.4.2  ATL
        3. 8.4.4.3  CSI
          1. 8.4.4.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 8.4.4.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 8.4.4.4  CPSW2G
        5. 8.4.4.5  CPSW9G
        6. 8.4.4.6  DCC
        7. 8.4.4.7  DDRSS
        8. 8.4.4.8  DSS
          1. 8.4.4.8.1 DSI
          2. 8.4.4.8.2 eDP
        9. 8.4.4.9  VPFE
        10. 8.4.4.10 eCAP
        11. 8.4.4.11 EPWM
        12. 8.4.4.12 ELM
        13. 8.4.4.13 ESM
        14. 8.4.4.14 eQEP
        15. 8.4.4.15 GPIO
        16. 8.4.4.16 GPMC
        17. 8.4.4.17 Hyperbus
        18. 8.4.4.18 I2C
        19. 8.4.4.19 I3C
        20. 8.4.4.20 MCAN
        21. 8.4.4.21 MCASP
        22. 8.4.4.22 MCRC Controller
        23. 8.4.4.23 MCSPI
        24. 8.4.4.24 MMC/SD
        25. 8.4.4.25 OSPI
        26. 8.4.4.26 PCIE
        27. 8.4.4.27 SerDes
        28. 8.4.4.28 WWDT
        29. 8.4.4.29 Timers
        30. 8.4.4.30 UART
        31. 8.4.4.31 USB
        32. 8.4.4.32 UFS
  9. Applications and Implementation
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide for AM752x/DRA829/TDA4VM Devices
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 SERDES REFCLK Design Guidelines
      4. 9.3.4 USB VBUS Design Guidelines
      5. 9.3.5 System Power Supply Monitor Design Guidelines
      6. 9.3.6 High Speed Differential Signal Routing Guidance
      7. 9.3.7 External Capacitors
      8. 9.3.8 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ALF|827
サーマルパッド・メカニカル・データ
発注情報

Pin Attributes

Note:

MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. BOOTMODE pins are latched on the rising edge of PORz_OUT.

Note:

Media Local Bus (MLB) is not available on this device. The following balls must be left unconnected if not used in GPIO mode: AE2, AD2, AD3, AC3, AC1, AD1.

Note:

PRU_ICSSG0 and PRU_ICSSG1 are not available on this device. The prg* signals should not be used. Those pins can be used for other functions.

Table 6-1 Pin Attributes
BALL NUMBER 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE 4 TYPE 5 BALL RESET STATE 6 BALL RESET REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/DOWN TYPE 12 DSIS 13 RXACTIVE/TXDISABLE 14
U7 CAP_VDDS0 CAP_VDDS0 CAP
K23 CAP_VDDS0_MCU CAP_VDDS0_MCU CAP
AB21 CAP_VDDS1 CAP_VDDS1 CAP
J18 CAP_VDDS1_MCU CAP_VDDS1_MCU CAP
Y18 CAP_VDDS2 CAP_VDDS2 CAP
J19 CAP_VDDS2_MCU CAP_VDDS2_MCU CAP
W21 CAP_VDDS3 CAP_VDDS3 CAP
AA22 CAP_VDDS4 CAP_VDDS4 CAP
R22 CAP_VDDS5 CAP_VDDS5 CAP
V22 CAP_VDDS6 CAP_VDDS6 CAP
B20 CSI0_RXCLKN CSI0_RXCLKN I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
A21 CSI0_RXCLKP CSI0_RXCLKP I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
F16 csi0_rxrcalib CSI0_RXRCALIB A OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
F15 csi1_rxrcalib CSI1_RXRCALIB A OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
B17 CSI1_RXCLKN CSI1_RXCLKN I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
A18 CSI1_RXCLKP CSI1_RXCLKP I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
B19 CSI0_RXN0 CSI0_RXN0 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
D18 CSI0_RXN1 CSI0_RXN1 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
D17 CSI0_RXN2 CSI0_RXN2 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
E16 CSI0_RXN3 CSI0_RXN3 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
A20 CSI0_RXP0 CSI0_RXP0 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
C19 CSI0_RXP1 CSI0_RXP1 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
C18 CSI0_RXP2 CSI0_RXP2 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
E17 CSI0_RXP3 CSI0_RXP3 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
B16 CSI1_RXN0 CSI1_RXN0 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
D15 CSI1_RXN1 CSI1_RXN1 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
D14 CSI1_RXN2 CSI1_RXN2 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
E13 CSI1_RXN3 CSI1_RXN3 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
A17 CSI1_RXP0 CSI1_RXP0 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
C16 CSI1_RXP1 CSI1_RXP1 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
C15 CSI1_RXP2 CSI1_RXP2 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
E14 CSI1_RXP3 CSI1_RXP3 I OFF 1.8 V VDDA_0P8_CSIRX / VDDA_1P8_CSIRX D-PHY
J1 ddr0_ckn DDR0_CKN IO OFF 1.1 V VDDS_DDR DDR0
H1 ddr0_ckp DDR0_CKP IO OFF 1.1 V VDDS_DDR DDR0
K6 ddr0_resetn DDR0_RESETn IO OFF 1.1 V VDDS_DDR DDR0
G4 ddr0_ca0 DDR0_CA0 IO OFF 1.1 V VDDS_DDR DDR0
H3 ddr0_ca1 DDR0_CA1 IO OFF 1.1 V VDDS_DDR DDR0
K5 ddr0_ca2 DDR0_CA2 IO OFF 1.1 V VDDS_DDR DDR0
J4 ddr0_ca3 DDR0_CA3 IO OFF 1.1 V VDDS_DDR DDR0
K2 ddr0_ca4 DDR0_CA4 IO OFF 1.1 V VDDS_DDR DDR0
H5 ddr0_ca5 DDR0_CA5 IO OFF 1.1 V VDDS_DDR DDR0
H2 ddr0_cal0 DDR0_CAL0 A OFF 1.1 V VDDS_DDR DDR0
G3 ddr0_cke0 DDR0_CKE0 IO OFF 1.1 V VDDS_DDR DDR0
J3 ddr0_cke1 DDR0_CKE1 IO OFF 1.1 V VDDS_DDR DDR0
J5 ddr0_csn0_0 DDR0_CSn0_0 IO OFF 1.1 V VDDS_DDR DDR0
K3 ddr0_csn0_1 DDR0_CSn0_1 IO OFF 1.1 V VDDS_DDR DDR0
G5 ddr0_csn1_0 DDR0_CSn1_0 IO OFF 1.1 V VDDS_DDR DDR0
J2 ddr0_csn1_1 DDR0_CSn1_1 IO OFF 1.1 V VDDS_DDR DDR0
A3 ddr0_dm0 DDR0_DM0 IO OFF 1.1 V VDDS_DDR DDR0
E4 ddr0_dm1 DDR0_DM1 IO OFF 1.1 V VDDS_DDR DDR0
N1 ddr0_dm2 DDR0_DM2 IO OFF 1.1 V VDDS_DDR DDR0
R5 ddr0_dm3 DDR0_DM3 IO OFF 1.1 V VDDS_DDR DDR0
A5 ddr0_dq0 DDR0_DQ0 IO OFF 1.1 V VDDS_DDR DDR0
A6 ddr0_dq1 DDR0_DQ1 IO OFF 1.1 V VDDS_DDR DDR0
B5 ddr0_dq2 DDR0_DQ2 IO OFF 1.1 V VDDS_DDR DDR0
C2 ddr0_dq3 DDR0_DQ3 IO OFF 1.1 V VDDS_DDR DDR0
B4 ddr0_dq4 DDR0_DQ4 IO OFF 1.1 V VDDS_DDR DDR0
C3 ddr0_dq5 DDR0_DQ5 IO OFF 1.1 V VDDS_DDR DDR0
A2 ddr0_dq6 DDR0_DQ6 IO OFF 1.1 V VDDS_DDR DDR0
A4 ddr0_dq7 DDR0_DQ7 IO OFF 1.1 V VDDS_DDR DDR0
D1 ddr0_dq8 DDR0_DQ8 IO OFF 1.1 V VDDS_DDR DDR0
C4 ddr0_dq9 DDR0_DQ9 IO OFF 1.1 V VDDS_DDR DDR0
F1 ddr0_dq10 DDR0_DQ10 IO OFF 1.1 V VDDS_DDR DDR0
G2 ddr0_dq11 DDR0_DQ11 IO OFF 1.1 V VDDS_DDR DDR0
F2 ddr0_dq12 DDR0_DQ12 IO OFF 1.1 V VDDS_DDR DDR0
F3 ddr0_dq13 DDR0_DQ13 IO OFF 1.1 V VDDS_DDR DDR0
D3 ddr0_dq14 DDR0_DQ14 IO OFF 1.1 V VDDS_DDR DDR0
F5 ddr0_dq15 DDR0_DQ15 IO OFF 1.1 V VDDS_DDR DDR0
L5 ddr0_dq16 DDR0_DQ16 IO OFF 1.1 V VDDS_DDR DDR0
M5 ddr0_dq17 DDR0_DQ17 IO OFF 1.1 V VDDS_DDR DDR0
N5 ddr0_dq18 DDR0_DQ18 IO OFF 1.1 V VDDS_DDR DDR0
L4 ddr0_dq19 DDR0_DQ19 IO OFF 1.1 V VDDS_DDR DDR0
L2 ddr0_dq20 DDR0_DQ20 IO OFF 1.1 V VDDS_DDR DDR0
L1 ddr0_dq21 DDR0_DQ21 IO OFF 1.1 V VDDS_DDR DDR0
N2 ddr0_dq22 DDR0_DQ22 IO OFF 1.1 V VDDS_DDR DDR0
N4 ddr0_dq23 DDR0_DQ23 IO OFF 1.1 V VDDS_DDR DDR0
T3 ddr0_dq24 DDR0_DQ24 IO OFF 1.1 V VDDS_DDR DDR0
T2 ddr0_dq25 DDR0_DQ25 IO OFF 1.1 V VDDS_DDR DDR0
P2 ddr0_dq26 DDR0_DQ26 IO OFF 1.1 V VDDS_DDR DDR0
P3 ddr0_dq27 DDR0_DQ27 IO OFF 1.1 V VDDS_DDR DDR0
P5 ddr0_dq28 DDR0_DQ28 IO OFF 1.1 V VDDS_DDR DDR0
R4 ddr0_dq29 DDR0_DQ29 IO OFF 1.1 V VDDS_DDR DDR0
T4 ddr0_dq30 DDR0_DQ30 IO OFF 1.1 V VDDS_DDR DDR0
T5 ddr0_dq31 DDR0_DQ31 IO OFF 1.1 V VDDS_DDR DDR0
B1 ddr0_dqs0n DDR0_DQS0N IO OFF 1.1 V VDDS_DDR DDR0
B2 ddr0_dqs0p DDR0_DQS0P IO OFF 1.1 V VDDS_DDR DDR0
E2 ddr0_dqs1n DDR0_DQS1N IO OFF 1.1 V VDDS_DDR DDR0
E3 ddr0_dqs1p DDR0_DQS1P IO OFF 1.1 V VDDS_DDR DDR0
M2 ddr0_dqs2n DDR0_DQS2N IO OFF 1.1 V VDDS_DDR DDR0
M3 ddr0_dqs2p DDR0_DQS2P IO OFF 1.1 V VDDS_DDR DDR0
R1 ddr0_dqs3n DDR0_DQS3N IO OFF 1.1 V VDDS_DDR DDR0
R2 ddr0_dqs3p DDR0_DQS3P IO OFF 1.1 V VDDS_DDR DDR0
P6 ddr_ret DDR_RET I OFF 1.1 V VDDS_DDR_BIAS DDR0
G6 dp0_auxn DP0_AUXN IO OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP AUX-PHY
F7 dp0_auxp DP0_AUXP IO OFF 0.8 V VDDA_0P8_DP / VDDA_1P8_DP AUX-PHY
E10 DSI_TXCLKN DSI_TXCLKN O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
E11 DSI_TXCLKP DSI_TXCLKP O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
D11 DSI_TXN0 DSI_TXN0 IO OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
D12 DSI_TXN1 DSI_TXN1 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
B13 DSI_TXN2 DSI_TXN2 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
B14 DSI_TXN3 DSI_TXN3 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
C12 DSI_TXP0 DSI_TXP0 IO OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
C13 DSI_TXP1 DSI_TXP1 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
A14 DSI_TXP2 DSI_TXP2 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
A15 DSI_TXP3 DSI_TXP3 O OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
F12 dsi_txrcalib DSI_TXRCALIB A OFF 1.8 V VDDA_0P8_DSITX / VDDA_1P8_DSITX D-PHY
U2 ecap0_in_apwm_out ECAP0_IN_APWM_OUT 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
SYNC0_OUT 1 O
CPTS0_RFT_CLK 2 I 0
SPI2_CS3 4 IO 1
I3C0_SDAPULLEN 5 O
SPI7_CS0 6 IO 1
GPIO1_11 7 IO 0
C26 emu0 EMU0 0 IO PU 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
B29 emu1 EMU1 0 IO PU 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
AC18 extintn EXTINTn 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes I2C OD FS 1 0/0
GPIO0_0 7 IO 0
U3 ext_refclk1 EXT_REFCLK1 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1
SYNC1_OUT 1 O
SPI7_CLK 6 IO 0
GPIO1_12 7 IO 0
AC5 i2c0_scl I2C0_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0
GPIO1_7 7 IO 0
AA5 i2c0_sda I2C0_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0
GPIO1_8 7 IO 0
Y6 i2c1_scl I2C1_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0
CPTS0_HW1TSPUSH 1 I 0
GPIO1_9 7 IO 0
AA6 i2c1_sda I2C1_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0
CPTS0_HW2TSPUSH 1 I 0
GPIO1_10 7 IO 0
W2 i3c0_scl I3C0_SCL 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
MMC2_SDCD 1 I 1
UART9_CTSn 2 I 1
MCAN2_RX 3 I 1
I2C6_SCL 4 IOD 1
DP0_HPD 5 I 0
PCIE0_CLKREQn 6 IO 0
GPIO1_5 7 IO 0
UART6_RXD 8 I 0
W1 i3c0_sda I3C0_SDA 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
MMC2_SDWP 1 I 1
UART9_RTSn 2 O
MCAN2_TX 3 O
I2C6_SDA 4 IOD 1
PCIE1_CLKREQn 6 IO 0
GPIO1_6 7 IO 0
UART6_TXD 8 O 0
W5 mcan0_rx MCAN0_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
I2C2_SCL 4 IOD 1
GPIO1_1 7 IO 0
W6 mcan0_tx MCAN0_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1
I2C2_SDA 4 IOD 1
GPIO1_2 7 IO 0
W3 mcan1_rx MCAN1_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1
UART6_CTSn 1 I 1
UART9_RXD 2 I 1
USB0_DRVVBUS 3 O
USB1_DRVVBUS 4 O
GPIO1_3 7 IO 0
V4 mcan1_tx MCAN1_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1
UART6_RTSn 1 O
UART9_TXD 2 O
USB0_DRVVBUS 3 O
USB1_DRVVBUS 4 O
GPIO1_4 7 IO 0
K25 mcu_adc0_ain0 MCU_ADC0_AIN0 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
K26 mcu_adc0_ain1 MCU_ADC0_AIN1 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
K28 mcu_adc0_ain2 MCU_ADC0_AIN2 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
L28 mcu_adc0_ain3 MCU_ADC0_AIN3 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
K24 mcu_adc0_ain4 MCU_ADC0_AIN4 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
K27 mcu_adc0_ain5 MCU_ADC0_AIN5 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
K29 mcu_adc0_ain6 MCU_ADC0_AIN6 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
L29 mcu_adc0_ain7 MCU_ADC0_AIN7 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B
N23 mcu_adc1_ain0 MCU_ADC1_AIN0 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
M25 mcu_adc1_ain1 MCU_ADC1_AIN1 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
L24 mcu_adc1_ain2 MCU_ADC1_AIN2 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
L26 mcu_adc1_ain3 MCU_ADC1_AIN3 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
N24 mcu_adc1_ain4 MCU_ADC1_AIN4 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
M24 mcu_adc1_ain5 MCU_ADC1_AIN5 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
L25 mcu_adc1_ain6 MCU_ADC1_AIN6 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
L27 mcu_adc1_ain7 MCU_ADC1_AIN7 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B
J26 mcu_i2c0_scl MCU_I2C0_SCL 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 1/0
WKUP_GPIO0_64 7 IO 0
H25 mcu_i2c0_sda MCU_I2C0_SDA 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 1/0
WKUP_GPIO0_65 7 IO 0
D26 mcu_i3c0_scl MCU_I3C0_SCL 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_UART0_CTSn 2 I 1
MCU_TIMER_IO8 4 IO 0
WKUP_GPIO0_60 7 IO 0
D25 mcu_i3c0_sda MCU_I3C0_SDA 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_UART0_RTSn 2 O
MCU_TIMER_IO9 4 IO 0
WKUP_GPIO0_61 7 IO 0
C29 mcu_mcan0_rx MCU_MCAN0_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 0/1
WKUP_GPIO0_59 7 IO 0
D29 mcu_mcan0_tx MCU_MCAN0_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/1
WKUP_GPIO0_58 7 IO 0
F23 mcu_mdio0_mdc MCU_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
WKUP_GPIO0_51 7 IO 0
E23 mcu_mdio0_mdio MCU_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
WKUP_GPIO0_50 7 IO 0
E20 mcu_ospi0_clk MCU_OSPI0_CLK 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
MCU_HYPERBUS0_CK 1 O
WKUP_GPIO0_16 7 IO 0
D21 mcu_ospi0_dqs MCU_OSPI0_DQS 0 I OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_RWDS 1 IO 0
WKUP_GPIO0_18 7 IO 0
C21 mcu_ospi0_lbclko MCU_OSPI0_LBCLKO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/1
MCU_HYPERBUS0_CKn 1 O
WKUP_GPIO0_17 7 IO 0
F22 mcu_ospi1_clk MCU_OSPI1_CLK 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
WKUP_GPIO0_29 7 IO 0
B23 mcu_ospi1_dqs MCU_OSPI1_DQS 0 I OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_OSPI0_CSn3 1 O
MCU_HYPERBUS0_INTn 2 I 1
MCU_OSPI0_ECC_FAIL 6 I 1
WKUP_GPIO0_31 7 IO 0
A23 mcu_ospi1_lbclko MCU_OSPI1_LBCLKO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/1
MCU_OSPI0_CSn2 1 O
MCU_HYPERBUS0_RESETOn 2 I 1
MCU_OSPI0_RESET_OUT0 6 O
WKUP_GPIO0_30 7 IO 0
F19 mcu_ospi0_csn0 MCU_OSPI0_CSn0 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
MCU_HYPERBUS0_CSn0 1 O
WKUP_GPIO0_27 7 IO 0
E19 mcu_ospi0_csn1 MCU_OSPI0_CSn1 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
MCU_HYPERBUS0_RESETn 1 O
WKUP_GPIO0_28 7 IO 0
D20 mcu_ospi0_d0 MCU_OSPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ0 1 IO 0
WKUP_GPIO0_19 7 IO 0
G19 mcu_ospi0_d1 MCU_OSPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ1 1 IO 0
WKUP_GPIO0_20 7 IO 0
G20 mcu_ospi0_d2 MCU_OSPI0_D2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ2 1 IO 0
WKUP_GPIO0_21 7 IO 0
F20 mcu_ospi0_d3 MCU_OSPI0_D3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ3 1 IO 0
WKUP_GPIO0_22 7 IO 0
F21 mcu_ospi0_d4 MCU_OSPI0_D4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ4 1 IO 0
WKUP_GPIO0_23 7 IO 0
E21 mcu_ospi0_d5 MCU_OSPI0_D5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ5 1 IO 0
WKUP_GPIO0_24 7 IO 0
B22 mcu_ospi0_d6 MCU_OSPI0_D6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ6 1 IO 0
WKUP_GPIO0_25 7 IO 0
G21 mcu_ospi0_d7 MCU_OSPI0_D7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_HYPERBUS0_DQ7 1 IO 0
WKUP_GPIO0_26 7 IO 0
C22 mcu_ospi1_csn0 MCU_OSPI1_CSn0 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
WKUP_GPIO0_36 7 IO 0
E22 mcu_ospi1_csn1 MCU_OSPI1_CSn1 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0/1
MCU_HYPERBUS0_WPn 1 O
MCU_TIMER_IO0 2 IO 0
MCU_HYPERBUS0_CSn1 3 O
MCU_UART0_RTSn 4 O
MCU_SPI0_CS2 5 IO 1
MCU_OSPI0_RESET_OUT1 6 O
WKUP_GPIO0_37 7 IO 0
D22 mcu_ospi1_d0 MCU_OSPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
WKUP_GPIO0_32 7 IO 0
G22 mcu_ospi1_d1 MCU_OSPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_UART0_RXD 4 I 1
MCU_SPI1_CS1 5 IO 1
WKUP_GPIO0_33 7 IO 0
D23 mcu_ospi1_d2 MCU_OSPI1_D2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_UART0_TXD 4 O
MCU_SPI1_CS2 5 IO 1
WKUP_GPIO0_34 7 IO 0
C23 mcu_ospi1_d3 MCU_OSPI1_D3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 0/1
MCU_UART0_CTSn 4 I 1
MCU_SPI0_CS1 5 IO 1
WKUP_GPIO0_35 7 IO 0
H23 mcu_porz MCU_PORz I OFF 1.8 V VDDA_WKUP Yes LVCMOS PU/PD
B28 mcu_porz_out MCU_PORz_OUT 0 O OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
C27 mcu_resetstatz MCU_RESETSTATz 0 O OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
D28 mcu_resetz MCU_RESETz 0 I PU 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/1
C24 mcu_rgmii1_rxc MCU_RGMII1_RXC 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_REF_CLK 1 I 0
WKUP_GPIO0_45 7 IO 0
C25 mcu_rgmii1_rx_ctl MCU_RGMII1_RX_CTL 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_RX_ER 1 I 0
WKUP_GPIO0_39 7 IO 0
B26 mcu_rgmii1_txc MCU_RGMII1_TXC 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_TX_EN 1 O
WKUP_GPIO0_44 7 IO 0
B27 mcu_rgmii1_tx_ctl MCU_RGMII1_TX_CTL 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_RMII1_CRS_DV 1 I 0
WKUP_GPIO0_38 7 IO 0
B24 mcu_rgmii1_rd0 MCU_RGMII1_RD0 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_RXD0 1 I 0
WKUP_GPIO0_49 7 IO 0
A24 mcu_rgmii1_rd1 MCU_RGMII1_RD1 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_RMII1_RXD1 1 I 0
WKUP_GPIO0_48 7 IO 0
D24 mcu_rgmii1_rd2 MCU_RGMII1_RD2 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_TIMER_IO5 1 IO 0
WKUP_GPIO0_47 7 IO 0
A25 mcu_rgmii1_rd3 MCU_RGMII1_RD3 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 0/1
MCU_TIMER_IO4 1 IO 0
WKUP_GPIO0_46 7 IO 0
B25 mcu_rgmii1_td0 MCU_RGMII1_TD0 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_RMII1_TXD0 1 O
WKUP_GPIO0_43 7 IO 0
A26 mcu_rgmii1_td1 MCU_RGMII1_TD1 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_RMII1_TXD1 1 O
WKUP_GPIO0_42 7 IO 0
A27 mcu_rgmii1_td2 MCU_RGMII1_TD2 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_TIMER_IO3 1 IO 0
MCU_ADC_EXT_TRIGGER1 3 I 0
WKUP_GPIO0_41 7 IO 0
A28 mcu_rgmii1_td3 MCU_RGMII1_TD3 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0/1
MCU_TIMER_IO2 1 IO 0
MCU_ADC_EXT_TRIGGER0 3 I 0
WKUP_GPIO0_40 7 IO 0
D27 mcu_safety_errorn MCU_SAFETY_ERRORn 0 IO PD 0 1.8 V VDDA_WKUP Yes LVCMOS PU/PD 1/0
E27 mcu_spi0_clk MCU_SPI0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/1
WKUP_GPIO0_52 7 IO 0
MCU_BOOTMODE00 Bootstrap I
E25 mcu_spi0_cs0 MCU_SPI0_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 0/1
MCU_TIMER_IO1 4 IO 0
WKUP_GPIO0_55 7 IO 0
E24 mcu_spi0_d0 MCU_SPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/1
WKUP_GPIO0_53 7 IO 0
MCU_BOOTMODE01 Bootstrap I
E28 mcu_spi0_d1 MCU_SPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/1
MCU_TIMER_IO0 4 IO 0
WKUP_GPIO0_54 7 IO 0
MCU_BOOTMODE02 Bootstrap I
V24 mdio0_mdc MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1
TRC_DATA23 5 O
GPIO0_110 7 IO 0
GPMC0_WAIT2 8 I 0
V26 mdio0_mdio MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1
TRC_DATA22 5 O
GPIO0_109 7 IO 0
GPMC0_WAIT3 8 I 0
AE2 mlb0_mlbcn MLB0_MLBCN 0 I OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_35 7 IO 0
AD2 mlb0_mlbcp MLB0_MLBCP 0 I OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_34 7 IO 0
AD3 mlb0_mlbdn MLB0_MLBDN 0 IO OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_33 7 IO 0
AC3 mlb0_mlbdp MLB0_MLBDP 0 IO OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_32 7 IO 0
AC1 mlb0_mlbsn MLB0_MLBSN 0 IO OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_31 7 IO 0
AD1 mlb0_mlbsp MLB0_MLBSP 0 IO OFF 0 1.8 V VDDA_1P8_MLB MLB_LVDS
GPIO1_30 7 IO 0
AE1 mmc0_calpad MMC0_CALPAD A OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AF1 mmc0_clk MMC0_CLK O OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AE3 mmc0_cmd MMC0_CMD IO OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AE4 mmc0_ds MMC0_DS IO OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
P25 mmc1_clk MMC1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 0 0/1
UART8_RXD 1 I 1
I2C4_SCL 4 IOD 1
GPIO1_19 7 IO 0
R29 mmc1_cmd MMC1_CMD 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART8_TXD 1 O
I2C4_SDA 4 IOD 1
GPIO1_20 7 IO 0
P23 mmc1_sdcd MMC1_SDCD 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 1 0/1
UART8_CTSn 1 I 1
UART0_DCDn 2 I 1
TIMER_IO2 3 IO 0
EQEP2_I 5 IO 0
PCIE2_CLKREQn 6 IO 0
GPIO1_21 7 IO 0
PRG0_IEP0_EDC_LATCH_IN1 8 I 0
R28 mmc1_sdwp MMC1_SDWP 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 1 0/1
UART8_RTSn 1 O
UART0_DSRn 2 I 1
TIMER_IO3 3 IO 0
ECAP2_IN_APWM_OUT 4 IO 0
EQEP2_S 5 IO 0
PCIE3_CLKREQn 6 IO 0
GPIO1_22 7 IO 0
PRG0_IEP0_EDC_SYNC_OUT1 8 O 0
T26 mmc2_clk MMC2_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 0 0/1
USB0_DRVVBUS 1 O
USB1_DRVVBUS 2 O
TIMER_IO6 3 IO 0
I2C3_SCL 4 IOD 1
UART3_RXD 5 I 1
GPIO1_27 7 IO 0
T25 mmc2_cmd MMC2_CMD 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
USB0_DRVVBUS 1 O
USB1_DRVVBUS 2 O
TIMER_IO7 3 IO 0
I2C3_SDA 4 IOD 1
UART3_TXD 5 O
GPIO1_28 7 IO 0
AG2 mmc0_dat0 MMC0_DAT0 IO OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AH1 mmc0_dat1 MMC0_DAT1 IO OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AG3 mmc0_dat2 MMC0_DAT2 IO OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AF4 mmc0_dat3 MMC0_DAT3 IO OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AE5 mmc0_dat4 MMC0_DAT4 IO OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AF3 mmc0_dat5 MMC0_DAT5 IO OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AG1 mmc0_dat6 MMC0_DAT6 IO OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1
AF2 mmc0_dat7 MMC0_DAT7 IO OFF 1.8 V VDDS_MMC0 eMMCPHY 1
R24 mmc1_dat0 MMC1_DAT0 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART7_RTSn 1 O
ECAP1_IN_APWM_OUT 2 IO 0
TIMER_IO1 3 IO 0
UART4_TXD 5 O
GPIO1_18 7 IO 0
P24 mmc1_dat1 MMC1_DAT1 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART7_CTSn 1 I 1
ECAP0_IN_APWM_OUT 2 IO 0
TIMER_IO0 3 IO 0
UART4_RXD 5 I 1
GPIO1_17 7 IO 0
R25 mmc1_dat2 MMC1_DAT2 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART7_TXD 1 O
GPIO1_16 7 IO 0
R26 mmc1_dat3 MMC1_DAT3 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1
UART7_RXD 1 I 1
GPIO1_15 7 IO 0
T24 mmc2_dat0 MMC2_DAT0 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
UART9_RTSn 1 O
UART0_RIn 2 I 1
TIMER_IO5 3 IO 0
UART6_TXD 4 O
EQEP2_B 5 I 0
GPIO1_26 7 IO 0
PRG0_IEP1_EDC_SYNC_OUT1 8 O 0
T27 mmc2_dat1 MMC2_DAT1 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
UART9_CTSn 1 I 1
UART0_DTRn 2 O
TIMER_IO4 3 IO 0
UART6_RXD 4 I 1
EQEP2_A 5 I 0
GPIO1_25 7 IO 0
PRG0_IEP1_EDC_LATCH_IN1 8 I 0
T29 mmc2_dat2 MMC2_DAT2 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
UART9_TXD 1 O
CPTS0_HW2TSPUSH 2 I 0
I2C5_SDA 4 IOD 1
GPIO1_24 7 IO 0
T28 mmc2_dat3 MMC2_DAT3 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1
UART9_RXD 1 I 1
CPTS0_HW1TSPUSH 2 I 0
I2C5_SCL 4 IOD 1
GPIO1_23 7 IO 0
P29 osc1_xi OSC1_XI I OFF 1.8 V VDDS_OSC1 HFOSC
P27 osc1_xo OSC1_XO O OFF 1.8 V VDDS_OSC1 HFOSC
AE17 pcie_refclk0n PCIE_REFCLK0N IO OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AD16 pcie_refclk0p PCIE_REFCLK0P IO OFF 0.8 V VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AE14 pcie_refclk1n PCIE_REFCLK1N IO OFF 0.8 V  VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AD15 pcie_refclk1p PCIE_REFCLK1P IO OFF 0.8 V  VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AE11 pcie_refclk2n PCIE_REFCLK2N IO OFF 0.8 V  VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AD12 pcie_refclk2p PCIE_REFCLK2P IO OFF 0.8 V  VDDA_0P8_SERDES0_1 / VDDA_1P8_SERDES0_1 2-L-PHY
AE9 pcie_refclk3n PCIE_REFCLK3N IO OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
AD10 pcie_refclk3p PCIE_REFCLK3P IO OFF 0.8 V  VDDA_0P8_SERDES2_3 / VDDA_1P8_SERDES2_3 2-L-PHY
E26 pmic_power_en0 MCU_I3C0_SDAPULLEN 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
WKUP_GPIO0_66 7 IO 0
G23 pmic_power_en1 PMIC_POWER_EN1 0 O OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
MCU_I3C1_SDAPULLEN 5 O
WKUP_GPIO0_67 7 IO 0
J24 porz PORz 0 I OFF 0 1.8 V VDDA_WKUP Yes LVCMOS PU/PD
U1 porz_out PORz_OUT 0 O OFF 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/0
AA27 prg0_mdio0_mdc PRG0_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0/1
I2C5_SDA 2 IOD 1
MCAN13_RX 6 I 1
GPIO0_84 7 IO 0
GPMC0_A0 8 OZ 0
DSS_FSYNC2 10 O
MCASP2_ACLKR 12 IO
MCASP2_AXR5 13 IO 0
Y26 prg0_mdio0_mdio PRG0_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
I2C5_SCL 2 IOD 1
MCAN13_TX 6 O
GPIO0_83 7 IO 0
GPMC0_A27 8 OZ 0
DSS_FSYNC0 10 O
MCASP2_AFSR 12 IO
MCASP2_AXR4 13 IO 0
AF28 prg0_pru0_gpo0 PRG0_PRU0_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI0 1 I 0
PRG0_RGMII1_RD0 2 I 0
PRG0_PWM3_A0 3 IO 0
RGMII3_RD0 4 I 0
RMII3_RXD1 5 I 0
GPIO0_43 7 IO 0
MCASP0_AXR0 12 IO
AE28 prg0_pru0_gpo1 PRG0_PRU0_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI1 1 I 0
PRG0_RGMII1_RD1 2 I 0
PRG0_PWM3_B0 3 IO 1
RGMII3_RD1 4 I 0
RMII3_RXD0 5 I 0
GPIO0_44 7 IO 0
MCASP0_AXR1 12 IO
AE27 prg0_pru0_gpo2 PRG0_PRU0_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI2 1 I 0
PRG0_RGMII1_RD2 2 I 0
PRG0_PWM2_A0 3 IO 0
RGMII3_RD2 4 I 0
RMII3_CRS_DV 5 I 0
GPIO0_45 7 IO 0
UART3_RXD 8 I 0
MCASP0_ACLKR 12 IO
AD26 prg0_pru0_gpo3 PRG0_PRU0_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI3 1 I 0
PRG0_RGMII1_RD3 2 I 0
PRG0_PWM3_A2 3 IO 0
RGMII3_RD3 4 I 0
RMII3_RX_ER 5 I 0
GPIO0_46 7 IO 0
UART3_TXD 8 O 0
MCASP0_AFSR 12 IO
AD25 prg0_pru0_gpo4 PRG0_PRU0_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI4 1 I 0
PRG0_RGMII1_RX_CTL 2 I 0
PRG0_PWM2_B0 3 IO 1
RGMII3_RX_CTL 4 I 0
RMII3_TXD1 5 O
GPIO0_47 7 IO 0
MCASP0_AXR2 12 IO
AC29 prg0_pru0_gpo5 PRG0_PRU0_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 1/1
PRG0_PRU0_GPI5 1 I 0
PRG0_PWM3_B2 3 IO 1
RMII3_TXD0 5 O
GPIO0_48 7 IO 0
GPMC0_AD0 8 IO 0
MCASP0_AXR3 12 IO
BOOTMODE2 Bootstrap I
AE26 prg0_pru0_gpo6 PRG0_PRU0_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI6 1 I 0
PRG0_RGMII1_RXC 2 I 0
PRG0_PWM3_A1 3 IO 0
RGMII3_RXC 4 I 0
RMII3_TX_EN 5 O
GPIO0_49 7 IO 0
MCASP0_AXR4 12 IO
AC28 prg0_pru0_gpo7 PRG0_PRU0_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI7 1 I 0
PRG0_IEP0_EDC_LATCH_IN1 2 I 0
PRG0_PWM3_B1 3 IO 1
PRG0_ECAP0_SYNC_IN 4 I 0
MCAN9_TX 6 O
GPIO0_50 7 IO 0
GPMC0_AD1 8 IO 0
MCASP0_AXR5 12 IO
AC27 prg0_pru0_gpo8 PRG0_PRU0_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI8 1 I 0
PRG0_PWM2_A1 3 IO 0
MCAN9_RX 6 I 1
GPIO0_51 7 IO 0
GPMC0_AD2 8 IO 0
MCASP0_AXR6 12 IO
UART6_RXD 14 I
AB26 prg0_pru0_gpo9 PRG0_PRU0_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1
PRG0_PRU0_GPI9 1 I 0
PRG0_UART0_CTSn 2 I 1
PRG0_PWM3_TZ_IN 3 I 0
SPI3_CS1 4 IO 1
PRG0_IEP0_EDIO_DATA_IN_OUT28 5 IO 0
MCAN10_TX 6 O
GPIO0_52 7 IO 0
GPMC0_AD3